/* * Copyright (c) 2013 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ /* */ /* File: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg_map_macro.h*/ /* Creator: irshad */ /* Time: Wednesday Feb 15, 2012 [5:06:37 pm] */ /* */ /* Path: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ /* Arguments: /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -dump */ /* -codegen */ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.codegen*/ /* -ath_ansic -Wdesc -I */ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ /* -I /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint */ /* -I */ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint*/ /* -I */ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig*/ /* -odir */ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ /* -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval */ /* $WAR_EV58615_for_ansic_codegen=1 scorpion_reg.rdl */ /* */ /* Sources: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/ /* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm*/ /* /cad/local/lib/perl/Pinfo.pm */ /* */ /* Blueprint: 3.7.3 (Fri Aug 29 12:39:16 PDT 2008) */ /* Machine: rupavathi.users.atheros.com */ /* OS: Linux 2.6.9-89.ELsmp */ /* Description: */ /* */ /*This Register Map contains the complete register set for scorpion. */ /* */ /* Copyright (C) 2012 Denali Software Inc. All rights reserved */ /* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ /* */ #ifndef __REG_SCORPION_REG_MAP_MACRO_H__ #define __REG_SCORPION_REG_MAP_MACRO_H__ /* macros for BlueprintGlobalNameSpace::MAC_DMA_CR */ #ifndef __MAC_DMA_CR_MACRO__ #define __MAC_DMA_CR_MACRO__ /* macros for field RXE_LP */ #define MAC_DMA_CR__RXE_LP__SHIFT 2 #define MAC_DMA_CR__RXE_LP__WIDTH 1 #define MAC_DMA_CR__RXE_LP__MASK 0x00000004U #define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) #define MAC_DMA_CR__RXE_LP__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_DMA_CR__RXE_LP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field RXE_HP */ #define MAC_DMA_CR__RXE_HP__SHIFT 3 #define MAC_DMA_CR__RXE_HP__WIDTH 1 #define MAC_DMA_CR__RXE_HP__MASK 0x00000008U #define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) #define MAC_DMA_CR__RXE_HP__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_DMA_CR__RXE_HP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field RXD */ #define MAC_DMA_CR__RXD__SHIFT 5 #define MAC_DMA_CR__RXD__WIDTH 1 #define MAC_DMA_CR__RXD__MASK 0x00000020U #define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) #define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) #define MAC_DMA_CR__RXD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_DMA_CR__RXD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_DMA_CR__RXD__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_DMA_CR__RXD__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field SWI */ #define MAC_DMA_CR__SWI__SHIFT 6 #define MAC_DMA_CR__SWI__WIDTH 1 #define MAC_DMA_CR__SWI__MASK 0x00000040U #define MAC_DMA_CR__SWI__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) #define MAC_DMA_CR__SWI__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_DMA_CR__SWI__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field SPARE */ #define MAC_DMA_CR__SPARE__SHIFT 7 #define MAC_DMA_CR__SPARE__WIDTH 4 #define MAC_DMA_CR__SPARE__MASK 0x00000780U #define MAC_DMA_CR__SPARE__READ(src) (((u_int32_t)(src) & 0x00000780U) >> 7) #define MAC_DMA_CR__SPARE__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000780U) #define MAC_DMA_CR__SPARE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000780U) | (((u_int32_t)(src) <<\ 7) & 0x00000780U) #define MAC_DMA_CR__SPARE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000780U))) #define MAC_DMA_CR__TYPE u_int32_t #define MAC_DMA_CR__READ 0x000007ecU #define MAC_DMA_CR__WRITE 0x000007ecU #endif /* __MAC_DMA_CR_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_CR */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_CR__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_CFG */ #ifndef __MAC_DMA_CFG_MACRO__ #define __MAC_DMA_CFG_MACRO__ /* macros for field BE_MODE_XMIT_DESC */ #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SHIFT 0 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WIDTH 1 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MASK 0x00000001U #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field BE_MODE_XMIT_DATA */ #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SHIFT 1 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WIDTH 1 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MASK 0x00000002U #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field BE_MODE_RCV_DESC */ #define MAC_DMA_CFG__BE_MODE_RCV_DESC__SHIFT 2 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__WIDTH 1 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__MASK 0x00000004U #define MAC_DMA_CFG__BE_MODE_RCV_DESC__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_DMA_CFG__BE_MODE_RCV_DESC__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_DMA_CFG__BE_MODE_RCV_DESC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_DMA_CFG__BE_MODE_RCV_DESC__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_DMA_CFG__BE_MODE_RCV_DESC__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field BE_MODE_RCV_DATA */ #define MAC_DMA_CFG__BE_MODE_RCV_DATA__SHIFT 3 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__WIDTH 1 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__MASK 0x00000008U #define MAC_DMA_CFG__BE_MODE_RCV_DATA__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_DMA_CFG__BE_MODE_RCV_DATA__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_DMA_CFG__BE_MODE_RCV_DATA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_DMA_CFG__BE_MODE_RCV_DATA__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_DMA_CFG__BE_MODE_RCV_DATA__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field BE_MODE_MMR */ #define MAC_DMA_CFG__BE_MODE_MMR__SHIFT 4 #define MAC_DMA_CFG__BE_MODE_MMR__WIDTH 1 #define MAC_DMA_CFG__BE_MODE_MMR__MASK 0x00000010U #define MAC_DMA_CFG__BE_MODE_MMR__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_DMA_CFG__BE_MODE_MMR__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_DMA_CFG__BE_MODE_MMR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_DMA_CFG__BE_MODE_MMR__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_DMA_CFG__BE_MODE_MMR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field ADHOC */ #define MAC_DMA_CFG__ADHOC__SHIFT 5 #define MAC_DMA_CFG__ADHOC__WIDTH 1 #define MAC_DMA_CFG__ADHOC__MASK 0x00000020U #define MAC_DMA_CFG__ADHOC__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) #define MAC_DMA_CFG__ADHOC__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) #define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_DMA_CFG__ADHOC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_DMA_CFG__ADHOC__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_DMA_CFG__ADHOC__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field PHY_OK */ #define MAC_DMA_CFG__PHY_OK__SHIFT 8 #define MAC_DMA_CFG__PHY_OK__WIDTH 1 #define MAC_DMA_CFG__PHY_OK__MASK 0x00000100U #define MAC_DMA_CFG__PHY_OK__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) #define MAC_DMA_CFG__PHY_OK__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_DMA_CFG__PHY_OK__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field EEPROM_BUSY */ #define MAC_DMA_CFG__EEPROM_BUSY__SHIFT 9 #define MAC_DMA_CFG__EEPROM_BUSY__WIDTH 1 #define MAC_DMA_CFG__EEPROM_BUSY__MASK 0x00000200U #define MAC_DMA_CFG__EEPROM_BUSY__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_DMA_CFG__EEPROM_BUSY__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_DMA_CFG__EEPROM_BUSY__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field CLKGATE_DIS */ #define MAC_DMA_CFG__CLKGATE_DIS__SHIFT 10 #define MAC_DMA_CFG__CLKGATE_DIS__WIDTH 1 #define MAC_DMA_CFG__CLKGATE_DIS__MASK 0x00000400U #define MAC_DMA_CFG__CLKGATE_DIS__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_DMA_CFG__CLKGATE_DIS__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_DMA_CFG__CLKGATE_DIS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_DMA_CFG__CLKGATE_DIS__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_DMA_CFG__CLKGATE_DIS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field HALT_REQ */ #define MAC_DMA_CFG__HALT_REQ__SHIFT 11 #define MAC_DMA_CFG__HALT_REQ__WIDTH 1 #define MAC_DMA_CFG__HALT_REQ__MASK 0x00000800U #define MAC_DMA_CFG__HALT_REQ__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_DMA_CFG__HALT_REQ__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_DMA_CFG__HALT_REQ__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_DMA_CFG__HALT_REQ__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_DMA_CFG__HALT_REQ__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field HALT_ACK */ #define MAC_DMA_CFG__HALT_ACK__SHIFT 12 #define MAC_DMA_CFG__HALT_ACK__WIDTH 1 #define MAC_DMA_CFG__HALT_ACK__MASK 0x00001000U #define MAC_DMA_CFG__HALT_ACK__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_DMA_CFG__HALT_ACK__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_DMA_CFG__HALT_ACK__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field REQ_Q_FULL_THRESHOLD */ #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__SHIFT 17 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WIDTH 2 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MASK 0x00060000U #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__READ(src) \ (((u_int32_t)(src)\ & 0x00060000U) >> 17) #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00060000U) #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00060000U) | (((u_int32_t)(src) <<\ 17) & 0x00060000U) #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00060000U))) /* macros for field MISSING_TX_INTR_FIX_ENABLE */ #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SHIFT 19 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WIDTH 1 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MASK 0x00080000U #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field LEGACY_INT_MIT_MODE_ENABLE */ #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SHIFT 20 #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WIDTH 1 #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MASK 0x00100000U #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field RESET_INT_MIT_CNTRS */ #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SHIFT 21 #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WIDTH 1 #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MASK 0x00200000U #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) #define MAC_DMA_CFG__TYPE u_int32_t #define MAC_DMA_CFG__READ 0x003e1f3fU #define MAC_DMA_CFG__WRITE 0x003e1f3fU #endif /* __MAC_DMA_CFG_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_CFG */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_CFG__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RXBUFPTR_THRESH */ #ifndef __MAC_DMA_RXBUFPTR_THRESH_MACRO__ #define __MAC_DMA_RXBUFPTR_THRESH_MACRO__ /* macros for field HP_DATA */ #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__SHIFT 0 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WIDTH 4 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MASK 0x0000000fU #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__READ(src) \ (u_int32_t)(src)\ & 0x0000000fU #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000000fU) #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000000fU))) /* macros for field LP_DATA */ #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__SHIFT 8 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WIDTH 7 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MASK 0x00007f00U #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__READ(src) \ (((u_int32_t)(src)\ & 0x00007f00U) >> 8) #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00007f00U) #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00007f00U) | (((u_int32_t)(src) <<\ 8) & 0x00007f00U) #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00007f00U))) #define MAC_DMA_RXBUFPTR_THRESH__TYPE u_int32_t #define MAC_DMA_RXBUFPTR_THRESH__READ 0x00007f0fU #define MAC_DMA_RXBUFPTR_THRESH__WRITE 0x00007f0fU #endif /* __MAC_DMA_RXBUFPTR_THRESH_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RXBUFPTR_THRESH */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RXBUFPTR_THRESH__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TXDPPTR_THRESH */ #ifndef __MAC_DMA_TXDPPTR_THRESH_MACRO__ #define __MAC_DMA_TXDPPTR_THRESH_MACRO__ /* macros for field DATA */ #define MAC_DMA_TXDPPTR_THRESH__DATA__SHIFT 0 #define MAC_DMA_TXDPPTR_THRESH__DATA__WIDTH 4 #define MAC_DMA_TXDPPTR_THRESH__DATA__MASK 0x0000000fU #define MAC_DMA_TXDPPTR_THRESH__DATA__READ(src) (u_int32_t)(src) & 0x0000000fU #define MAC_DMA_TXDPPTR_THRESH__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000000fU) #define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_DMA_TXDPPTR_THRESH__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000000fU))) #define MAC_DMA_TXDPPTR_THRESH__TYPE u_int32_t #define MAC_DMA_TXDPPTR_THRESH__READ 0x0000000fU #define MAC_DMA_TXDPPTR_THRESH__WRITE 0x0000000fU #endif /* __MAC_DMA_TXDPPTR_THRESH_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TXDPPTR_THRESH */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TXDPPTR_THRESH__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_MIRT */ #ifndef __MAC_DMA_MIRT_MACRO__ #define __MAC_DMA_MIRT_MACRO__ /* macros for field RATE_THRESH */ #define MAC_DMA_MIRT__RATE_THRESH__SHIFT 0 #define MAC_DMA_MIRT__RATE_THRESH__WIDTH 16 #define MAC_DMA_MIRT__RATE_THRESH__MASK 0x0000ffffU #define MAC_DMA_MIRT__RATE_THRESH__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_DMA_MIRT__RATE_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_MIRT__RATE_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_DMA_MIRT__TYPE u_int32_t #define MAC_DMA_MIRT__READ 0x0000ffffU #define MAC_DMA_MIRT__WRITE 0x0000ffffU #endif /* __MAC_DMA_MIRT_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_MIRT */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_MIRT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_GLOBAL_IER */ #ifndef __MAC_DMA_GLOBAL_IER_MACRO__ #define __MAC_DMA_GLOBAL_IER_MACRO__ /* macros for field ENABLE */ #define MAC_DMA_GLOBAL_IER__ENABLE__SHIFT 0 #define MAC_DMA_GLOBAL_IER__ENABLE__WIDTH 1 #define MAC_DMA_GLOBAL_IER__ENABLE__MASK 0x00000001U #define MAC_DMA_GLOBAL_IER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_DMA_GLOBAL_IER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_DMA_GLOBAL_IER__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_DMA_GLOBAL_IER__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_DMA_GLOBAL_IER__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) #define MAC_DMA_GLOBAL_IER__TYPE u_int32_t #define MAC_DMA_GLOBAL_IER__READ 0x00000001U #define MAC_DMA_GLOBAL_IER__WRITE 0x00000001U #endif /* __MAC_DMA_GLOBAL_IER_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_GLOBAL_IER */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_GLOBAL_IER__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_alias */ #ifndef __MAC_DMA_TIMT_ALIAS_MACRO__ #define __MAC_DMA_TIMT_ALIAS_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_ALIAS__TYPE u_int32_t #define MAC_DMA_TIMT_ALIAS__READ 0xffffffffU #define MAC_DMA_TIMT_ALIAS__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_ALIAS_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RIMT */ #ifndef __MAC_DMA_RIMT_MACRO__ #define __MAC_DMA_RIMT_MACRO__ /* macros for field RX_LAST_PKT_THRESH */ #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field RX_FIRST_PKT_THRESH */ #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_RIMT__TYPE u_int32_t #define MAC_DMA_RIMT__READ 0xffffffffU #define MAC_DMA_RIMT__WRITE 0xffffffffU #endif /* __MAC_DMA_RIMT_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RIMT */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RIMT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TXCFG */ #ifndef __MAC_DMA_TXCFG_MACRO__ #define __MAC_DMA_TXCFG_MACRO__ /* macros for field DMA_SIZE */ #define MAC_DMA_TXCFG__DMA_SIZE__SHIFT 0 #define MAC_DMA_TXCFG__DMA_SIZE__WIDTH 3 #define MAC_DMA_TXCFG__DMA_SIZE__MASK 0x00000007U #define MAC_DMA_TXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U #define MAC_DMA_TXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) #define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000007U) | ((u_int32_t)(src) &\ 0x00000007U) #define MAC_DMA_TXCFG__DMA_SIZE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000007U))) /* macros for field TRIGLVL */ #define MAC_DMA_TXCFG__TRIGLVL__SHIFT 4 #define MAC_DMA_TXCFG__TRIGLVL__WIDTH 6 #define MAC_DMA_TXCFG__TRIGLVL__MASK 0x000003f0U #define MAC_DMA_TXCFG__TRIGLVL__READ(src) \ (((u_int32_t)(src)\ & 0x000003f0U) >> 4) #define MAC_DMA_TXCFG__TRIGLVL__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x000003f0U) #define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003f0U) | (((u_int32_t)(src) <<\ 4) & 0x000003f0U) #define MAC_DMA_TXCFG__TRIGLVL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x000003f0U))) /* macros for field JUMBO_EN */ #define MAC_DMA_TXCFG__JUMBO_EN__SHIFT 10 #define MAC_DMA_TXCFG__JUMBO_EN__WIDTH 1 #define MAC_DMA_TXCFG__JUMBO_EN__MASK 0x00000400U #define MAC_DMA_TXCFG__JUMBO_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_DMA_TXCFG__JUMBO_EN__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_DMA_TXCFG__JUMBO_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_DMA_TXCFG__JUMBO_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_DMA_TXCFG__JUMBO_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field BCN_PAST_ATIM_DIS */ #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SHIFT 11 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WIDTH 1 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MASK 0x00000800U #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field ATIM_DEFER_DIS */ #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SHIFT 12 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WIDTH 1 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MASK 0x00001000U #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field RTCI_DIS */ #define MAC_DMA_TXCFG__RTCI_DIS__SHIFT 14 #define MAC_DMA_TXCFG__RTCI_DIS__WIDTH 1 #define MAC_DMA_TXCFG__RTCI_DIS__MASK 0x00004000U #define MAC_DMA_TXCFG__RTCI_DIS__READ(src) \ (((u_int32_t)(src)\ & 0x00004000U) >> 14) #define MAC_DMA_TXCFG__RTCI_DIS__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x00004000U) #define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00004000U) | (((u_int32_t)(src) <<\ 14) & 0x00004000U) #define MAC_DMA_TXCFG__RTCI_DIS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x00004000U))) #define MAC_DMA_TXCFG__RTCI_DIS__SET(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(1) << 14) #define MAC_DMA_TXCFG__RTCI_DIS__CLR(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(0) << 14) /* macros for field DIS_RETRY_UNDERRUN */ #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SHIFT 17 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WIDTH 1 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MASK 0x00020000U #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field DIS_CW_INC_QUIET_COLL */ #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SHIFT 18 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WIDTH 1 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MASK 0x00040000U #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field RTS_FAIL_EXCESSIVE_RETRIES */ #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SHIFT 19 #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WIDTH 1 #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MASK 0x00080000U #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) #define MAC_DMA_TXCFG__TYPE u_int32_t #define MAC_DMA_TXCFG__READ 0x000e5ff7U #define MAC_DMA_TXCFG__WRITE 0x000e5ff7U #endif /* __MAC_DMA_TXCFG_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TXCFG */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TXCFG__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RXCFG */ #ifndef __MAC_DMA_RXCFG_MACRO__ #define __MAC_DMA_RXCFG_MACRO__ /* macros for field DMA_SIZE */ #define MAC_DMA_RXCFG__DMA_SIZE__SHIFT 0 #define MAC_DMA_RXCFG__DMA_SIZE__WIDTH 3 #define MAC_DMA_RXCFG__DMA_SIZE__MASK 0x00000007U #define MAC_DMA_RXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U #define MAC_DMA_RXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) #define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000007U) | ((u_int32_t)(src) &\ 0x00000007U) #define MAC_DMA_RXCFG__DMA_SIZE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000007U))) /* macros for field ZERO_LEN_DMA_EN */ #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__SHIFT 3 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WIDTH 2 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MASK 0x00000018U #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000018U) >> 3) #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000018U) #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000018U) | (((u_int32_t)(src) <<\ 3) & 0x00000018U) #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000018U))) /* macros for field JUMBO_EN */ #define MAC_DMA_RXCFG__JUMBO_EN__SHIFT 5 #define MAC_DMA_RXCFG__JUMBO_EN__WIDTH 1 #define MAC_DMA_RXCFG__JUMBO_EN__MASK 0x00000020U #define MAC_DMA_RXCFG__JUMBO_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_DMA_RXCFG__JUMBO_EN__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_DMA_RXCFG__JUMBO_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_DMA_RXCFG__JUMBO_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_DMA_RXCFG__JUMBO_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field JUMBO_WRAP_EN */ #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SHIFT 6 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WIDTH 1 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MASK 0x00000040U #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field SLEEP_RX_PEND_EN */ #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SHIFT 7 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WIDTH 1 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MASK 0x00000080U #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) #define MAC_DMA_RXCFG__TYPE u_int32_t #define MAC_DMA_RXCFG__READ 0x000000ffU #define MAC_DMA_RXCFG__WRITE 0x000000ffU #endif /* __MAC_DMA_RXCFG_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RXCFG */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RXCFG__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RXJLA */ #ifndef __MAC_DMA_RXJLA_MACRO__ #define __MAC_DMA_RXJLA_MACRO__ /* macros for field DATA */ #define MAC_DMA_RXJLA__DATA__SHIFT 2 #define MAC_DMA_RXJLA__DATA__WIDTH 30 #define MAC_DMA_RXJLA__DATA__MASK 0xfffffffcU #define MAC_DMA_RXJLA__DATA__READ(src) (((u_int32_t)(src) & 0xfffffffcU) >> 2) #define MAC_DMA_RXJLA__TYPE u_int32_t #define MAC_DMA_RXJLA__READ 0xfffffffcU #endif /* __MAC_DMA_RXJLA_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RXJLA */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RXJLA__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_MIBC */ #ifndef __MAC_DMA_MIBC_MACRO__ #define __MAC_DMA_MIBC_MACRO__ /* macros for field WARNING */ #define MAC_DMA_MIBC__WARNING__SHIFT 0 #define MAC_DMA_MIBC__WARNING__WIDTH 1 #define MAC_DMA_MIBC__WARNING__MASK 0x00000001U #define MAC_DMA_MIBC__WARNING__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_DMA_MIBC__WARNING__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_DMA_MIBC__WARNING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field FREEZE */ #define MAC_DMA_MIBC__FREEZE__SHIFT 1 #define MAC_DMA_MIBC__FREEZE__WIDTH 1 #define MAC_DMA_MIBC__FREEZE__MASK 0x00000002U #define MAC_DMA_MIBC__FREEZE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) #define MAC_DMA_MIBC__FREEZE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_DMA_MIBC__FREEZE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_DMA_MIBC__FREEZE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_DMA_MIBC__FREEZE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field CLEAR */ #define MAC_DMA_MIBC__CLEAR__SHIFT 2 #define MAC_DMA_MIBC__CLEAR__WIDTH 1 #define MAC_DMA_MIBC__CLEAR__MASK 0x00000004U #define MAC_DMA_MIBC__CLEAR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) #define MAC_DMA_MIBC__CLEAR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) #define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_DMA_MIBC__CLEAR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_DMA_MIBC__CLEAR__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_DMA_MIBC__CLEAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field STROBE */ #define MAC_DMA_MIBC__STROBE__SHIFT 3 #define MAC_DMA_MIBC__STROBE__WIDTH 1 #define MAC_DMA_MIBC__STROBE__MASK 0x00000008U #define MAC_DMA_MIBC__STROBE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) #define MAC_DMA_MIBC__STROBE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_DMA_MIBC__STROBE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) #define MAC_DMA_MIBC__TYPE u_int32_t #define MAC_DMA_MIBC__READ 0x0000000fU #define MAC_DMA_MIBC__WRITE 0x0000000fU #endif /* __MAC_DMA_MIBC_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_MIBC */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_MIBC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TOPS */ #ifndef __MAC_DMA_TOPS_MACRO__ #define __MAC_DMA_TOPS_MACRO__ /* macros for field TIMEOUT */ #define MAC_DMA_TOPS__TIMEOUT__SHIFT 0 #define MAC_DMA_TOPS__TIMEOUT__WIDTH 16 #define MAC_DMA_TOPS__TIMEOUT__MASK 0x0000ffffU #define MAC_DMA_TOPS__TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_DMA_TOPS__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TOPS__TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_DMA_TOPS__TYPE u_int32_t #define MAC_DMA_TOPS__READ 0x0000ffffU #define MAC_DMA_TOPS__WRITE 0x0000ffffU #endif /* __MAC_DMA_TOPS_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TOPS */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TOPS__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RXNPTO */ #ifndef __MAC_DMA_RXNPTO_MACRO__ #define __MAC_DMA_RXNPTO_MACRO__ /* macros for field TIMEOUT */ #define MAC_DMA_RXNPTO__TIMEOUT__SHIFT 0 #define MAC_DMA_RXNPTO__TIMEOUT__WIDTH 10 #define MAC_DMA_RXNPTO__TIMEOUT__MASK 0x000003ffU #define MAC_DMA_RXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_DMA_RXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_DMA_RXNPTO__TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) #define MAC_DMA_RXNPTO__TYPE u_int32_t #define MAC_DMA_RXNPTO__READ 0x000003ffU #define MAC_DMA_RXNPTO__WRITE 0x000003ffU #endif /* __MAC_DMA_RXNPTO_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RXNPTO */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RXNPTO__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TXNPTO */ #ifndef __MAC_DMA_TXNPTO_MACRO__ #define __MAC_DMA_TXNPTO_MACRO__ /* macros for field TIMEOUT */ #define MAC_DMA_TXNPTO__TIMEOUT__SHIFT 0 #define MAC_DMA_TXNPTO__TIMEOUT__WIDTH 10 #define MAC_DMA_TXNPTO__TIMEOUT__MASK 0x000003ffU #define MAC_DMA_TXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_DMA_TXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_DMA_TXNPTO__TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) /* macros for field MASK */ #define MAC_DMA_TXNPTO__MASK__SHIFT 10 #define MAC_DMA_TXNPTO__MASK__WIDTH 10 #define MAC_DMA_TXNPTO__MASK__MASK 0x000ffc00U #define MAC_DMA_TXNPTO__MASK__READ(src) \ (((u_int32_t)(src)\ & 0x000ffc00U) >> 10) #define MAC_DMA_TXNPTO__MASK__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x000ffc00U) #define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000ffc00U) | (((u_int32_t)(src) <<\ 10) & 0x000ffc00U) #define MAC_DMA_TXNPTO__MASK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x000ffc00U))) #define MAC_DMA_TXNPTO__TYPE u_int32_t #define MAC_DMA_TXNPTO__READ 0x000fffffU #define MAC_DMA_TXNPTO__WRITE 0x000fffffU #endif /* __MAC_DMA_TXNPTO_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TXNPTO */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TXNPTO__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RPGTO */ #ifndef __MAC_DMA_RPGTO_MACRO__ #define __MAC_DMA_RPGTO_MACRO__ /* macros for field TIMEOUT */ #define MAC_DMA_RPGTO__TIMEOUT__SHIFT 0 #define MAC_DMA_RPGTO__TIMEOUT__WIDTH 10 #define MAC_DMA_RPGTO__TIMEOUT__MASK 0x000003ffU #define MAC_DMA_RPGTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_DMA_RPGTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_DMA_RPGTO__TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) #define MAC_DMA_RPGTO__TYPE u_int32_t #define MAC_DMA_RPGTO__READ 0x000003ffU #define MAC_DMA_RPGTO__WRITE 0x000003ffU #endif /* __MAC_DMA_RPGTO_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RPGTO */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RPGTO__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_MACMISC */ #ifndef __MAC_DMA_MACMISC_MACRO__ #define __MAC_DMA_MACMISC_MACRO__ /* macros for field FORCE_PCI_EXT */ #define MAC_DMA_MACMISC__FORCE_PCI_EXT__SHIFT 4 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__WIDTH 1 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__MASK 0x00000010U #define MAC_DMA_MACMISC__FORCE_PCI_EXT__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_DMA_MACMISC__FORCE_PCI_EXT__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_DMA_MACMISC__FORCE_PCI_EXT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_DMA_MACMISC__FORCE_PCI_EXT__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_DMA_MACMISC__FORCE_PCI_EXT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field DMA_OBS_MUXSEL */ #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__SHIFT 5 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WIDTH 4 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MASK 0x000001e0U #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__READ(src) \ (((u_int32_t)(src)\ & 0x000001e0U) >> 5) #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x000001e0U) #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000001e0U) | (((u_int32_t)(src) <<\ 5) & 0x000001e0U) #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x000001e0U))) /* macros for field MISC_OBS_MUXSEL */ #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__SHIFT 9 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WIDTH 3 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MASK 0x00000e00U #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000e00U) >> 9) #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000e00U) #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000e00U) | (((u_int32_t)(src) <<\ 9) & 0x00000e00U) #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000e00U))) /* macros for field MISC_F2_OBS_LOW_MUXSEL */ #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__SHIFT 12 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WIDTH 3 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MASK 0x00007000U #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__READ(src) \ (((u_int32_t)(src)\ & 0x00007000U) >> 12) #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00007000U) #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00007000U) | (((u_int32_t)(src) <<\ 12) & 0x00007000U) #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00007000U))) /* macros for field MISC_F2_OBS_HIGH_MUXSEL */ #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__SHIFT 15 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WIDTH 3 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MASK 0x00038000U #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__READ(src) \ (((u_int32_t)(src)\ & 0x00038000U) >> 15) #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WRITE(src) \ (((u_int32_t)(src)\ << 15) & 0x00038000U) #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00038000U) | (((u_int32_t)(src) <<\ 15) & 0x00038000U) #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 15) & ~0x00038000U))) #define MAC_DMA_MACMISC__TYPE u_int32_t #define MAC_DMA_MACMISC__READ 0x0003fff0U #define MAC_DMA_MACMISC__WRITE 0x0003fff0U #endif /* __MAC_DMA_MACMISC_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_MACMISC */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_MACMISC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_INTER */ #ifndef __MAC_DMA_INTER_MACRO__ #define __MAC_DMA_INTER_MACRO__ /* macros for field REQ */ #define MAC_DMA_INTER__REQ__SHIFT 0 #define MAC_DMA_INTER__REQ__WIDTH 1 #define MAC_DMA_INTER__REQ__MASK 0x00000001U #define MAC_DMA_INTER__REQ__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_DMA_INTER__REQ__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_DMA_INTER__REQ__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_DMA_INTER__REQ__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) #define MAC_DMA_INTER__REQ__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_DMA_INTER__REQ__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field MSI_RX_SRC */ #define MAC_DMA_INTER__MSI_RX_SRC__SHIFT 1 #define MAC_DMA_INTER__MSI_RX_SRC__WIDTH 2 #define MAC_DMA_INTER__MSI_RX_SRC__MASK 0x00000006U #define MAC_DMA_INTER__MSI_RX_SRC__READ(src) \ (((u_int32_t)(src)\ & 0x00000006U) >> 1) #define MAC_DMA_INTER__MSI_RX_SRC__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000006U) #define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000006U) | (((u_int32_t)(src) <<\ 1) & 0x00000006U) #define MAC_DMA_INTER__MSI_RX_SRC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000006U))) /* macros for field MSI_TX_SRC */ #define MAC_DMA_INTER__MSI_TX_SRC__SHIFT 3 #define MAC_DMA_INTER__MSI_TX_SRC__WIDTH 2 #define MAC_DMA_INTER__MSI_TX_SRC__MASK 0x00000018U #define MAC_DMA_INTER__MSI_TX_SRC__READ(src) \ (((u_int32_t)(src)\ & 0x00000018U) >> 3) #define MAC_DMA_INTER__MSI_TX_SRC__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000018U) #define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000018U) | (((u_int32_t)(src) <<\ 3) & 0x00000018U) #define MAC_DMA_INTER__MSI_TX_SRC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000018U))) #define MAC_DMA_INTER__TYPE u_int32_t #define MAC_DMA_INTER__READ 0x0000001fU #define MAC_DMA_INTER__WRITE 0x0000001fU #endif /* __MAC_DMA_INTER_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_INTER */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_INTER__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DATABUF */ #ifndef __MAC_DMA_DATABUF_MACRO__ #define __MAC_DMA_DATABUF_MACRO__ /* macros for field LEN */ #define MAC_DMA_DATABUF__LEN__SHIFT 0 #define MAC_DMA_DATABUF__LEN__WIDTH 12 #define MAC_DMA_DATABUF__LEN__MASK 0x00000fffU #define MAC_DMA_DATABUF__LEN__READ(src) (u_int32_t)(src) & 0x00000fffU #define MAC_DMA_DATABUF__LEN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) #define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000fffU) | ((u_int32_t)(src) &\ 0x00000fffU) #define MAC_DMA_DATABUF__LEN__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000fffU))) #define MAC_DMA_DATABUF__TYPE u_int32_t #define MAC_DMA_DATABUF__READ 0x00000fffU #define MAC_DMA_DATABUF__WRITE 0x00000fffU #endif /* __MAC_DMA_DATABUF_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DATABUF */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DATABUF__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_GTT */ #ifndef __MAC_DMA_GTT_MACRO__ #define __MAC_DMA_GTT_MACRO__ /* macros for field COUNT */ #define MAC_DMA_GTT__COUNT__SHIFT 0 #define MAC_DMA_GTT__COUNT__WIDTH 16 #define MAC_DMA_GTT__COUNT__MASK 0x0000ffffU #define MAC_DMA_GTT__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_DMA_GTT__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_GTT__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) /* macros for field LIMIT */ #define MAC_DMA_GTT__LIMIT__SHIFT 16 #define MAC_DMA_GTT__LIMIT__WIDTH 16 #define MAC_DMA_GTT__LIMIT__MASK 0xffff0000U #define MAC_DMA_GTT__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) #define MAC_DMA_GTT__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) #define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_GTT__LIMIT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_GTT__TYPE u_int32_t #define MAC_DMA_GTT__READ 0xffffffffU #define MAC_DMA_GTT__WRITE 0xffffffffU #endif /* __MAC_DMA_GTT_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_GTT */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_GTT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_GTTM */ #ifndef __MAC_DMA_GTTM_MACRO__ #define __MAC_DMA_GTTM_MACRO__ /* macros for field USEC_STROBE */ #define MAC_DMA_GTTM__USEC_STROBE__SHIFT 0 #define MAC_DMA_GTTM__USEC_STROBE__WIDTH 1 #define MAC_DMA_GTTM__USEC_STROBE__MASK 0x00000001U #define MAC_DMA_GTTM__USEC_STROBE__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_DMA_GTTM__USEC_STROBE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_DMA_GTTM__USEC_STROBE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_DMA_GTTM__USEC_STROBE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_DMA_GTTM__USEC_STROBE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field IGNORE_CHAN_IDLE */ #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SHIFT 1 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WIDTH 1 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MASK 0x00000002U #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field RESET_ON_CHAN_IDLE */ #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SHIFT 2 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WIDTH 1 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MASK 0x00000004U #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field CST_USEC_STROBE */ #define MAC_DMA_GTTM__CST_USEC_STROBE__SHIFT 3 #define MAC_DMA_GTTM__CST_USEC_STROBE__WIDTH 1 #define MAC_DMA_GTTM__CST_USEC_STROBE__MASK 0x00000008U #define MAC_DMA_GTTM__CST_USEC_STROBE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_DMA_GTTM__CST_USEC_STROBE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_DMA_GTTM__CST_USEC_STROBE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_DMA_GTTM__CST_USEC_STROBE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_DMA_GTTM__CST_USEC_STROBE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field DISABLE_QCU_FR_ACTIVE_GTT */ #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SHIFT 4 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WIDTH 1 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MASK 0x00000010U #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field DISABLE_QCU_FR_ACTIVE_BT */ #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SHIFT 5 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WIDTH 1 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MASK 0x00000020U #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) #define MAC_DMA_GTTM__TYPE u_int32_t #define MAC_DMA_GTTM__READ 0x0000003fU #define MAC_DMA_GTTM__WRITE 0x0000003fU #endif /* __MAC_DMA_GTTM_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_GTTM */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_GTTM__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_CST */ #ifndef __MAC_DMA_CST_MACRO__ #define __MAC_DMA_CST_MACRO__ /* macros for field COUNT */ #define MAC_DMA_CST__COUNT__SHIFT 0 #define MAC_DMA_CST__COUNT__WIDTH 16 #define MAC_DMA_CST__COUNT__MASK 0x0000ffffU #define MAC_DMA_CST__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_DMA_CST__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_DMA_CST__COUNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_CST__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) /* macros for field LIMIT */ #define MAC_DMA_CST__LIMIT__SHIFT 16 #define MAC_DMA_CST__LIMIT__WIDTH 16 #define MAC_DMA_CST__LIMIT__MASK 0xffff0000U #define MAC_DMA_CST__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) #define MAC_DMA_CST__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) #define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_CST__LIMIT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_CST__TYPE u_int32_t #define MAC_DMA_CST__READ 0xffffffffU #define MAC_DMA_CST__WRITE 0xffffffffU #endif /* __MAC_DMA_CST_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_CST */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_CST__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RXDP_SIZE */ #ifndef __MAC_DMA_RXDP_SIZE_MACRO__ #define __MAC_DMA_RXDP_SIZE_MACRO__ /* macros for field LP */ #define MAC_DMA_RXDP_SIZE__LP__SHIFT 0 #define MAC_DMA_RXDP_SIZE__LP__WIDTH 8 #define MAC_DMA_RXDP_SIZE__LP__MASK 0x000000ffU #define MAC_DMA_RXDP_SIZE__LP__READ(src) (u_int32_t)(src) & 0x000000ffU /* macros for field HP */ #define MAC_DMA_RXDP_SIZE__HP__SHIFT 8 #define MAC_DMA_RXDP_SIZE__HP__WIDTH 5 #define MAC_DMA_RXDP_SIZE__HP__MASK 0x00001f00U #define MAC_DMA_RXDP_SIZE__HP__READ(src) \ (((u_int32_t)(src)\ & 0x00001f00U) >> 8) #define MAC_DMA_RXDP_SIZE__TYPE u_int32_t #define MAC_DMA_RXDP_SIZE__READ 0x00001fffU #endif /* __MAC_DMA_RXDP_SIZE_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RXDP_SIZE */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RXDP_SIZE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_HP_RXDP */ #ifndef __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ #define __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ /* macros for field ADDR */ #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__SHIFT 0 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WIDTH 32 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MASK 0xffffffffU #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_RX_QUEUE_HP_RXDP__TYPE u_int32_t #define MAC_DMA_RX_QUEUE_HP_RXDP__READ 0xffffffffU #define MAC_DMA_RX_QUEUE_HP_RXDP__WRITE 0xffffffffU #endif /* __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_HP_RXDP */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_HP_RXDP__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_LP_RXDP */ #ifndef __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ #define __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ /* macros for field ADDR */ #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__SHIFT 0 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WIDTH 32 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MASK 0xffffffffU #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_RX_QUEUE_LP_RXDP__TYPE u_int32_t #define MAC_DMA_RX_QUEUE_LP_RXDP__READ 0xffffffffU #define MAC_DMA_RX_QUEUE_LP_RXDP__WRITE 0xffffffffU #endif /* __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_LP_RXDP */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_LP_RXDP__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P */ #ifndef __MAC_DMA_ISR_P_MACRO__ #define __MAC_DMA_ISR_P_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_P__DATA__SHIFT 0 #define MAC_DMA_ISR_P__DATA__WIDTH 32 #define MAC_DMA_ISR_P__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_P__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_P__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_ISR_P__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) #define MAC_DMA_ISR_P__TYPE u_int32_t #define MAC_DMA_ISR_P__READ 0xffffffffU #define MAC_DMA_ISR_P__WRITE 0xffffffffU #endif /* __MAC_DMA_ISR_P_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_P */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0 */ #ifndef __MAC_DMA_ISR_S0_MACRO__ #define __MAC_DMA_ISR_S0_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_S0__DATA__SHIFT 0 #define MAC_DMA_ISR_S0__DATA__WIDTH 32 #define MAC_DMA_ISR_S0__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_S0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_ISR_S0__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_ISR_S0__TYPE u_int32_t #define MAC_DMA_ISR_S0__READ 0xffffffffU #define MAC_DMA_ISR_S0__WRITE 0xffffffffU #endif /* __MAC_DMA_ISR_S0_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S0 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1 */ #ifndef __MAC_DMA_ISR_S1_MACRO__ #define __MAC_DMA_ISR_S1_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_S1__DATA__SHIFT 0 #define MAC_DMA_ISR_S1__DATA__WIDTH 32 #define MAC_DMA_ISR_S1__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_ISR_S1__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_ISR_S1__TYPE u_int32_t #define MAC_DMA_ISR_S1__READ 0xffffffffU #define MAC_DMA_ISR_S1__WRITE 0xffffffffU #endif /* __MAC_DMA_ISR_S1_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S1 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2 */ #ifndef __MAC_DMA_ISR_S2_MACRO__ #define __MAC_DMA_ISR_S2_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_S2__DATA__SHIFT 0 #define MAC_DMA_ISR_S2__DATA__WIDTH 32 #define MAC_DMA_ISR_S2__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_S2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_ISR_S2__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_ISR_S2__TYPE u_int32_t #define MAC_DMA_ISR_S2__READ 0xffffffffU #define MAC_DMA_ISR_S2__WRITE 0xffffffffU #endif /* __MAC_DMA_ISR_S2_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S2 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3 */ #ifndef __MAC_DMA_ISR_S3_MACRO__ #define __MAC_DMA_ISR_S3_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_S3__DATA__SHIFT 0 #define MAC_DMA_ISR_S3__DATA__WIDTH 32 #define MAC_DMA_ISR_S3__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_S3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_ISR_S3__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_ISR_S3__TYPE u_int32_t #define MAC_DMA_ISR_S3__READ 0xffffffffU #define MAC_DMA_ISR_S3__WRITE 0xffffffffU #endif /* __MAC_DMA_ISR_S3_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S3 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4 */ #ifndef __MAC_DMA_ISR_S4_MACRO__ #define __MAC_DMA_ISR_S4_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_S4__DATA__SHIFT 0 #define MAC_DMA_ISR_S4__DATA__WIDTH 32 #define MAC_DMA_ISR_S4__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_S4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_ISR_S4__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_ISR_S4__TYPE u_int32_t #define MAC_DMA_ISR_S4__READ 0xffffffffU #define MAC_DMA_ISR_S4__WRITE 0xffffffffU #endif /* __MAC_DMA_ISR_S4_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S4 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5 */ #ifndef __MAC_DMA_ISR_S5_MACRO__ #define __MAC_DMA_ISR_S5_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_S5__DATA__SHIFT 0 #define MAC_DMA_ISR_S5__DATA__WIDTH 32 #define MAC_DMA_ISR_S5__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_S5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S5__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_ISR_S5__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_ISR_S5__TYPE u_int32_t #define MAC_DMA_ISR_S5__READ 0xffffffffU #define MAC_DMA_ISR_S5__WRITE 0xffffffffU #endif /* __MAC_DMA_ISR_S5_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S5 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_P */ #ifndef __MAC_DMA_IMR_P_MACRO__ #define __MAC_DMA_IMR_P_MACRO__ /* macros for field MASK */ #define MAC_DMA_IMR_P__MASK__SHIFT 0 #define MAC_DMA_IMR_P__MASK__WIDTH 32 #define MAC_DMA_IMR_P__MASK__MASK 0xffffffffU #define MAC_DMA_IMR_P__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_IMR_P__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_IMR_P__MASK__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) #define MAC_DMA_IMR_P__TYPE u_int32_t #define MAC_DMA_IMR_P__READ 0xffffffffU #define MAC_DMA_IMR_P__WRITE 0xffffffffU #endif /* __MAC_DMA_IMR_P_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_IMR_P */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_P__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S0 */ #ifndef __MAC_DMA_IMR_S0_MACRO__ #define __MAC_DMA_IMR_S0_MACRO__ /* macros for field MASK */ #define MAC_DMA_IMR_S0__MASK__SHIFT 0 #define MAC_DMA_IMR_S0__MASK__WIDTH 32 #define MAC_DMA_IMR_S0__MASK__MASK 0xffffffffU #define MAC_DMA_IMR_S0__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_IMR_S0__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_IMR_S0__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_IMR_S0__TYPE u_int32_t #define MAC_DMA_IMR_S0__READ 0xffffffffU #define MAC_DMA_IMR_S0__WRITE 0xffffffffU #endif /* __MAC_DMA_IMR_S0_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_IMR_S0 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S1 */ #ifndef __MAC_DMA_IMR_S1_MACRO__ #define __MAC_DMA_IMR_S1_MACRO__ /* macros for field DATA */ #define MAC_DMA_IMR_S1__DATA__SHIFT 0 #define MAC_DMA_IMR_S1__DATA__WIDTH 32 #define MAC_DMA_IMR_S1__DATA__MASK 0xffffffffU #define MAC_DMA_IMR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_IMR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_IMR_S1__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_IMR_S1__TYPE u_int32_t #define MAC_DMA_IMR_S1__READ 0xffffffffU #define MAC_DMA_IMR_S1__WRITE 0xffffffffU #endif /* __MAC_DMA_IMR_S1_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_IMR_S1 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S2 */ #ifndef __MAC_DMA_IMR_S2_MACRO__ #define __MAC_DMA_IMR_S2_MACRO__ /* macros for field MASK */ #define MAC_DMA_IMR_S2__MASK__SHIFT 0 #define MAC_DMA_IMR_S2__MASK__WIDTH 32 #define MAC_DMA_IMR_S2__MASK__MASK 0xffffffffU #define MAC_DMA_IMR_S2__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_IMR_S2__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_IMR_S2__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_IMR_S2__TYPE u_int32_t #define MAC_DMA_IMR_S2__READ 0xffffffffU #define MAC_DMA_IMR_S2__WRITE 0xffffffffU #endif /* __MAC_DMA_IMR_S2_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_IMR_S2 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S3 */ #ifndef __MAC_DMA_IMR_S3_MACRO__ #define __MAC_DMA_IMR_S3_MACRO__ /* macros for field MASK */ #define MAC_DMA_IMR_S3__MASK__SHIFT 0 #define MAC_DMA_IMR_S3__MASK__WIDTH 32 #define MAC_DMA_IMR_S3__MASK__MASK 0xffffffffU #define MAC_DMA_IMR_S3__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_IMR_S3__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_IMR_S3__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_IMR_S3__TYPE u_int32_t #define MAC_DMA_IMR_S3__READ 0xffffffffU #define MAC_DMA_IMR_S3__WRITE 0xffffffffU #endif /* __MAC_DMA_IMR_S3_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_IMR_S3 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S4 */ #ifndef __MAC_DMA_IMR_S4_MACRO__ #define __MAC_DMA_IMR_S4_MACRO__ /* macros for field MASK */ #define MAC_DMA_IMR_S4__MASK__SHIFT 0 #define MAC_DMA_IMR_S4__MASK__WIDTH 32 #define MAC_DMA_IMR_S4__MASK__MASK 0xffffffffU #define MAC_DMA_IMR_S4__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_IMR_S4__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_IMR_S4__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_IMR_S4__TYPE u_int32_t #define MAC_DMA_IMR_S4__READ 0xffffffffU #define MAC_DMA_IMR_S4__WRITE 0xffffffffU #endif /* __MAC_DMA_IMR_S4_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_IMR_S4 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S4__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S5 */ #ifndef __MAC_DMA_IMR_S5_MACRO__ #define __MAC_DMA_IMR_S5_MACRO__ /* macros for field MASK */ #define MAC_DMA_IMR_S5__MASK__SHIFT 0 #define MAC_DMA_IMR_S5__MASK__WIDTH 32 #define MAC_DMA_IMR_S5__MASK__MASK 0xffffffffU #define MAC_DMA_IMR_S5__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_IMR_S5__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DMA_IMR_S5__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DMA_IMR_S5__TYPE u_int32_t #define MAC_DMA_IMR_S5__READ 0xffffffffU #define MAC_DMA_IMR_S5__WRITE 0xffffffffU #endif /* __MAC_DMA_IMR_S5_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_IMR_S5 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S5__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P_RAC */ #ifndef __MAC_DMA_ISR_P_RAC_MACRO__ #define __MAC_DMA_ISR_P_RAC_MACRO__ /* macros for field DATA */ #define MAC_DMA_ISR_P_RAC__DATA__SHIFT 0 #define MAC_DMA_ISR_P_RAC__DATA__WIDTH 32 #define MAC_DMA_ISR_P_RAC__DATA__MASK 0xffffffffU #define MAC_DMA_ISR_P_RAC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_P_RAC__TYPE u_int32_t #define MAC_DMA_ISR_P_RAC__READ 0xffffffffU #endif /* __MAC_DMA_ISR_P_RAC_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_P_RAC */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P_RAC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0_S */ #ifndef __MAC_DMA_ISR_S0_S_MACRO__ #define __MAC_DMA_ISR_S0_S_MACRO__ /* macros for field SHADOW */ #define MAC_DMA_ISR_S0_S__SHADOW__SHIFT 0 #define MAC_DMA_ISR_S0_S__SHADOW__WIDTH 32 #define MAC_DMA_ISR_S0_S__SHADOW__MASK 0xffffffffU #define MAC_DMA_ISR_S0_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S0_S__TYPE u_int32_t #define MAC_DMA_ISR_S0_S__READ 0xffffffffU #endif /* __MAC_DMA_ISR_S0_S_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S0_S */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0_S__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1_S */ #ifndef __MAC_DMA_ISR_S1_S_MACRO__ #define __MAC_DMA_ISR_S1_S_MACRO__ /* macros for field SHADOW */ #define MAC_DMA_ISR_S1_S__SHADOW__SHIFT 0 #define MAC_DMA_ISR_S1_S__SHADOW__WIDTH 32 #define MAC_DMA_ISR_S1_S__SHADOW__MASK 0xffffffffU #define MAC_DMA_ISR_S1_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S1_S__TYPE u_int32_t #define MAC_DMA_ISR_S1_S__READ 0xffffffffU #endif /* __MAC_DMA_ISR_S1_S_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S1_S */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1_S__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2_S */ #ifndef __MAC_DMA_ISR_S2_S_MACRO__ #define __MAC_DMA_ISR_S2_S_MACRO__ /* macros for field SHADOW */ #define MAC_DMA_ISR_S2_S__SHADOW__SHIFT 0 #define MAC_DMA_ISR_S2_S__SHADOW__WIDTH 32 #define MAC_DMA_ISR_S2_S__SHADOW__MASK 0xffffffffU #define MAC_DMA_ISR_S2_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S2_S__TYPE u_int32_t #define MAC_DMA_ISR_S2_S__READ 0xffffffffU #endif /* __MAC_DMA_ISR_S2_S_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S2_S */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2_S__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3_S */ #ifndef __MAC_DMA_ISR_S3_S_MACRO__ #define __MAC_DMA_ISR_S3_S_MACRO__ /* macros for field SHADOW */ #define MAC_DMA_ISR_S3_S__SHADOW__SHIFT 0 #define MAC_DMA_ISR_S3_S__SHADOW__WIDTH 32 #define MAC_DMA_ISR_S3_S__SHADOW__MASK 0xffffffffU #define MAC_DMA_ISR_S3_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S3_S__TYPE u_int32_t #define MAC_DMA_ISR_S3_S__READ 0xffffffffU #endif /* __MAC_DMA_ISR_S3_S_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S3_S */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3_S__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4_S */ #ifndef __MAC_DMA_ISR_S4_S_MACRO__ #define __MAC_DMA_ISR_S4_S_MACRO__ /* macros for field SHADOW */ #define MAC_DMA_ISR_S4_S__SHADOW__SHIFT 0 #define MAC_DMA_ISR_S4_S__SHADOW__WIDTH 32 #define MAC_DMA_ISR_S4_S__SHADOW__MASK 0xffffffffU #define MAC_DMA_ISR_S4_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S4_S__TYPE u_int32_t #define MAC_DMA_ISR_S4_S__READ 0xffffffffU #endif /* __MAC_DMA_ISR_S4_S_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S4_S */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4_S__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5_S */ #ifndef __MAC_DMA_ISR_S5_S_MACRO__ #define __MAC_DMA_ISR_S5_S_MACRO__ /* macros for field SHADOW */ #define MAC_DMA_ISR_S5_S__SHADOW__SHIFT 0 #define MAC_DMA_ISR_S5_S__SHADOW__WIDTH 32 #define MAC_DMA_ISR_S5_S__SHADOW__MASK 0xffffffffU #define MAC_DMA_ISR_S5_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_ISR_S5_S__TYPE u_int32_t #define MAC_DMA_ISR_S5_S__READ 0xffffffffU #endif /* __MAC_DMA_ISR_S5_S_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_ISR_S5_S */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5_S__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_0 */ #ifndef __MAC_DMA_DMADBG_0_MACRO__ #define __MAC_DMA_DMADBG_0_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_0__DATA__SHIFT 0 #define MAC_DMA_DMADBG_0__DATA__WIDTH 32 #define MAC_DMA_DMADBG_0__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_0__TYPE u_int32_t #define MAC_DMA_DMADBG_0__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_0_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_0 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_1 */ #ifndef __MAC_DMA_DMADBG_1_MACRO__ #define __MAC_DMA_DMADBG_1_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_1__DATA__SHIFT 0 #define MAC_DMA_DMADBG_1__DATA__WIDTH 32 #define MAC_DMA_DMADBG_1__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_1__TYPE u_int32_t #define MAC_DMA_DMADBG_1__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_1_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_1 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_2 */ #ifndef __MAC_DMA_DMADBG_2_MACRO__ #define __MAC_DMA_DMADBG_2_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_2__DATA__SHIFT 0 #define MAC_DMA_DMADBG_2__DATA__WIDTH 32 #define MAC_DMA_DMADBG_2__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_2__TYPE u_int32_t #define MAC_DMA_DMADBG_2__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_2_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_2 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_3 */ #ifndef __MAC_DMA_DMADBG_3_MACRO__ #define __MAC_DMA_DMADBG_3_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_3__DATA__SHIFT 0 #define MAC_DMA_DMADBG_3__DATA__WIDTH 32 #define MAC_DMA_DMADBG_3__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_3__TYPE u_int32_t #define MAC_DMA_DMADBG_3__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_3_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_3 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_4 */ #ifndef __MAC_DMA_DMADBG_4_MACRO__ #define __MAC_DMA_DMADBG_4_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_4__DATA__SHIFT 0 #define MAC_DMA_DMADBG_4__DATA__WIDTH 32 #define MAC_DMA_DMADBG_4__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_4__TYPE u_int32_t #define MAC_DMA_DMADBG_4__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_4_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_4 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_4__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_5 */ #ifndef __MAC_DMA_DMADBG_5_MACRO__ #define __MAC_DMA_DMADBG_5_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_5__DATA__SHIFT 0 #define MAC_DMA_DMADBG_5__DATA__WIDTH 32 #define MAC_DMA_DMADBG_5__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_5__TYPE u_int32_t #define MAC_DMA_DMADBG_5__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_5_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_5 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_5__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_6 */ #ifndef __MAC_DMA_DMADBG_6_MACRO__ #define __MAC_DMA_DMADBG_6_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_6__DATA__SHIFT 0 #define MAC_DMA_DMADBG_6__DATA__WIDTH 32 #define MAC_DMA_DMADBG_6__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_6__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_6__TYPE u_int32_t #define MAC_DMA_DMADBG_6__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_6_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_6 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_6__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_7 */ #ifndef __MAC_DMA_DMADBG_7_MACRO__ #define __MAC_DMA_DMADBG_7_MACRO__ /* macros for field DATA */ #define MAC_DMA_DMADBG_7__DATA__SHIFT 0 #define MAC_DMA_DMADBG_7__DATA__WIDTH 32 #define MAC_DMA_DMADBG_7__DATA__MASK 0xffffffffU #define MAC_DMA_DMADBG_7__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DMA_DMADBG_7__TYPE u_int32_t #define MAC_DMA_DMADBG_7__READ 0xffffffffU #endif /* __MAC_DMA_DMADBG_7_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_DMADBG_7 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_7__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */ #ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ #define __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ /* macros for field DATA */ #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__SHIFT 0 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__WIDTH 32 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__MASK 0xffffffffU #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__TYPE u_int32_t #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__READ 0xffffffffU #endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */ #ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ #define __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ /* macros for field DATA */ #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__SHIFT 0 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__WIDTH 8 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__MASK 0x000000ffU #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__TYPE u_int32_t #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__READ 0x000000ffU #endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_0 */ #ifndef __MAC_DMA_TIMT_0_MACRO__ #define __MAC_DMA_TIMT_0_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_0__TYPE u_int32_t #define MAC_DMA_TIMT_0__READ 0xffffffffU #define MAC_DMA_TIMT_0__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_0_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_0 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_1 */ #ifndef __MAC_DMA_TIMT_1_MACRO__ #define __MAC_DMA_TIMT_1_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_1__TYPE u_int32_t #define MAC_DMA_TIMT_1__READ 0xffffffffU #define MAC_DMA_TIMT_1__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_1_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_1 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_2 */ #ifndef __MAC_DMA_TIMT_2_MACRO__ #define __MAC_DMA_TIMT_2_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_2__TYPE u_int32_t #define MAC_DMA_TIMT_2__READ 0xffffffffU #define MAC_DMA_TIMT_2__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_2_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_2 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_3 */ #ifndef __MAC_DMA_TIMT_3_MACRO__ #define __MAC_DMA_TIMT_3_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_3__TYPE u_int32_t #define MAC_DMA_TIMT_3__READ 0xffffffffU #define MAC_DMA_TIMT_3__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_3_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_3 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_4 */ #ifndef __MAC_DMA_TIMT_4_MACRO__ #define __MAC_DMA_TIMT_4_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_4__TYPE u_int32_t #define MAC_DMA_TIMT_4__READ 0xffffffffU #define MAC_DMA_TIMT_4__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_4_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_4 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_4__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_5 */ #ifndef __MAC_DMA_TIMT_5_MACRO__ #define __MAC_DMA_TIMT_5_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_5__TYPE u_int32_t #define MAC_DMA_TIMT_5__READ 0xffffffffU #define MAC_DMA_TIMT_5__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_5_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_5 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_5__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_6 */ #ifndef __MAC_DMA_TIMT_6_MACRO__ #define __MAC_DMA_TIMT_6_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_6__TYPE u_int32_t #define MAC_DMA_TIMT_6__READ 0xffffffffU #define MAC_DMA_TIMT_6__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_6_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_6 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_6__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_7 */ #ifndef __MAC_DMA_TIMT_7_MACRO__ #define __MAC_DMA_TIMT_7_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_7__TYPE u_int32_t #define MAC_DMA_TIMT_7__READ 0xffffffffU #define MAC_DMA_TIMT_7__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_7_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_7 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_7__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_8 */ #ifndef __MAC_DMA_TIMT_8_MACRO__ #define __MAC_DMA_TIMT_8_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_8__TYPE u_int32_t #define MAC_DMA_TIMT_8__READ 0xffffffffU #define MAC_DMA_TIMT_8__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_8_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_8 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_8__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_9 */ #ifndef __MAC_DMA_TIMT_9_MACRO__ #define __MAC_DMA_TIMT_9_MACRO__ /* macros for field TX_LAST_PKT_THRESH */ #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__SHIFT 0 #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MASK 0x0000ffffU #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field TX_FIRST_PKT_THRESH */ #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__SHIFT 16 #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WIDTH 16 #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MASK 0xffff0000U #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_DMA_TIMT_9__TYPE u_int32_t #define MAC_DMA_TIMT_9__READ 0xffffffffU #define MAC_DMA_TIMT_9__WRITE 0xffffffffU #endif /* __MAC_DMA_TIMT_9_MACRO__ */ /* macros for mac_dma_reg_map.MAC_DMA_TIMT_9 */ #define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_9__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_TXDP */ #ifndef __MAC_QCU_TXDP_MACRO__ #define __MAC_QCU_TXDP_MACRO__ /* macros for field DATA */ #define MAC_QCU_TXDP__DATA__SHIFT 0 #define MAC_QCU_TXDP__DATA__WIDTH 32 #define MAC_QCU_TXDP__DATA__MASK 0xffffffffU #define MAC_QCU_TXDP__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_QCU_TXDP__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_QCU_TXDP__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) #define MAC_QCU_TXDP__TYPE u_int32_t #define MAC_QCU_TXDP__READ 0xffffffffU #define MAC_QCU_TXDP__WRITE 0xffffffffU #endif /* __MAC_QCU_TXDP_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_TXDP */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_TXDP__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_START */ #ifndef __MAC_QCU_STATUS_RING_START_MACRO__ #define __MAC_QCU_STATUS_RING_START_MACRO__ /* macros for field ADDR */ #define MAC_QCU_STATUS_RING_START__ADDR__SHIFT 0 #define MAC_QCU_STATUS_RING_START__ADDR__WIDTH 32 #define MAC_QCU_STATUS_RING_START__ADDR__MASK 0xffffffffU #define MAC_QCU_STATUS_RING_START__ADDR__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_QCU_STATUS_RING_START__ADDR__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_QCU_STATUS_RING_START__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_QCU_STATUS_RING_START__TYPE u_int32_t #define MAC_QCU_STATUS_RING_START__READ 0xffffffffU #define MAC_QCU_STATUS_RING_START__WRITE 0xffffffffU #endif /* __MAC_QCU_STATUS_RING_START_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_START */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_START__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_END */ #ifndef __MAC_QCU_STATUS_RING_END_MACRO__ #define __MAC_QCU_STATUS_RING_END_MACRO__ /* macros for field ADDR */ #define MAC_QCU_STATUS_RING_END__ADDR__SHIFT 0 #define MAC_QCU_STATUS_RING_END__ADDR__WIDTH 32 #define MAC_QCU_STATUS_RING_END__ADDR__MASK 0xffffffffU #define MAC_QCU_STATUS_RING_END__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_QCU_STATUS_RING_END__ADDR__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_QCU_STATUS_RING_END__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_QCU_STATUS_RING_END__TYPE u_int32_t #define MAC_QCU_STATUS_RING_END__READ 0xffffffffU #define MAC_QCU_STATUS_RING_END__WRITE 0xffffffffU #endif /* __MAC_QCU_STATUS_RING_END_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_END */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_END__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_CURRENT */ #ifndef __MAC_QCU_STATUS_RING_CURRENT_MACRO__ #define __MAC_QCU_STATUS_RING_CURRENT_MACRO__ /* macros for field ADDRESS */ #define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__SHIFT 0 #define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__WIDTH 32 #define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__MASK 0xffffffffU #define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_QCU_STATUS_RING_CURRENT__TYPE u_int32_t #define MAC_QCU_STATUS_RING_CURRENT__READ 0xffffffffU #endif /* __MAC_QCU_STATUS_RING_CURRENT_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_CURRENT */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_CURRENT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_TXE */ #ifndef __MAC_QCU_TXE_MACRO__ #define __MAC_QCU_TXE_MACRO__ /* macros for field DATA */ #define MAC_QCU_TXE__DATA__SHIFT 0 #define MAC_QCU_TXE__DATA__WIDTH 10 #define MAC_QCU_TXE__DATA__MASK 0x000003ffU #define MAC_QCU_TXE__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_QCU_TXE__TYPE u_int32_t #define MAC_QCU_TXE__READ 0x000003ffU #endif /* __MAC_QCU_TXE_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_TXE */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_TXE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_TXD */ #ifndef __MAC_QCU_TXD_MACRO__ #define __MAC_QCU_TXD_MACRO__ /* macros for field DATA */ #define MAC_QCU_TXD__DATA__SHIFT 0 #define MAC_QCU_TXD__DATA__WIDTH 10 #define MAC_QCU_TXD__DATA__MASK 0x000003ffU #define MAC_QCU_TXD__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_QCU_TXD__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define MAC_QCU_TXD__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_QCU_TXD__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) /* macros for field SPARE */ #define MAC_QCU_TXD__SPARE__SHIFT 10 #define MAC_QCU_TXD__SPARE__WIDTH 4 #define MAC_QCU_TXD__SPARE__MASK 0x00003c00U #define MAC_QCU_TXD__SPARE__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10) #define MAC_QCU_TXD__SPARE__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U) #define MAC_QCU_TXD__SPARE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00003c00U) | (((u_int32_t)(src) <<\ 10) & 0x00003c00U) #define MAC_QCU_TXD__SPARE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00003c00U))) #define MAC_QCU_TXD__TYPE u_int32_t #define MAC_QCU_TXD__READ 0x00003fffU #define MAC_QCU_TXD__WRITE 0x00003fffU #endif /* __MAC_QCU_TXD_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_TXD */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_TXD__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_CBR */ #ifndef __MAC_QCU_CBR_MACRO__ #define __MAC_QCU_CBR_MACRO__ /* macros for field INTERVAL */ #define MAC_QCU_CBR__INTERVAL__SHIFT 0 #define MAC_QCU_CBR__INTERVAL__WIDTH 24 #define MAC_QCU_CBR__INTERVAL__MASK 0x00ffffffU #define MAC_QCU_CBR__INTERVAL__READ(src) (u_int32_t)(src) & 0x00ffffffU #define MAC_QCU_CBR__INTERVAL__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) #define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_QCU_CBR__INTERVAL__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) /* macros for field OVF_THRESH */ #define MAC_QCU_CBR__OVF_THRESH__SHIFT 24 #define MAC_QCU_CBR__OVF_THRESH__WIDTH 8 #define MAC_QCU_CBR__OVF_THRESH__MASK 0xff000000U #define MAC_QCU_CBR__OVF_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_QCU_CBR__OVF_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_QCU_CBR__OVF_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_QCU_CBR__TYPE u_int32_t #define MAC_QCU_CBR__READ 0xffffffffU #define MAC_QCU_CBR__WRITE 0xffffffffU #endif /* __MAC_QCU_CBR_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_CBR */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_CBR__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME */ #ifndef __MAC_QCU_RDYTIME_MACRO__ #define __MAC_QCU_RDYTIME_MACRO__ /* macros for field DURATION */ #define MAC_QCU_RDYTIME__DURATION__SHIFT 0 #define MAC_QCU_RDYTIME__DURATION__WIDTH 24 #define MAC_QCU_RDYTIME__DURATION__MASK 0x00ffffffU #define MAC_QCU_RDYTIME__DURATION__READ(src) (u_int32_t)(src) & 0x00ffffffU #define MAC_QCU_RDYTIME__DURATION__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) #define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_QCU_RDYTIME__DURATION__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) /* macros for field EN */ #define MAC_QCU_RDYTIME__EN__SHIFT 24 #define MAC_QCU_RDYTIME__EN__WIDTH 1 #define MAC_QCU_RDYTIME__EN__MASK 0x01000000U #define MAC_QCU_RDYTIME__EN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) #define MAC_QCU_RDYTIME__EN__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_QCU_RDYTIME__EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_QCU_RDYTIME__EN__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_QCU_RDYTIME__EN__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) #define MAC_QCU_RDYTIME__TYPE u_int32_t #define MAC_QCU_RDYTIME__READ 0x01ffffffU #define MAC_QCU_RDYTIME__WRITE 0x01ffffffU #endif /* __MAC_QCU_RDYTIME_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_SC */ #ifndef __MAC_QCU_ONESHOT_ARM_SC_MACRO__ #define __MAC_QCU_ONESHOT_ARM_SC_MACRO__ /* macros for field SET */ #define MAC_QCU_ONESHOT_ARM_SC__SET__SHIFT 0 #define MAC_QCU_ONESHOT_ARM_SC__SET__WIDTH 10 #define MAC_QCU_ONESHOT_ARM_SC__SET__MASK 0x000003ffU #define MAC_QCU_ONESHOT_ARM_SC__SET__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_QCU_ONESHOT_ARM_SC__SET__WRITE(src) \ ((u_int32_t)(src)\ & 0x000003ffU) #define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_QCU_ONESHOT_ARM_SC__SET__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) #define MAC_QCU_ONESHOT_ARM_SC__TYPE u_int32_t #define MAC_QCU_ONESHOT_ARM_SC__READ 0x000003ffU #define MAC_QCU_ONESHOT_ARM_SC__WRITE 0x000003ffU #endif /* __MAC_QCU_ONESHOT_ARM_SC_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_SC */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_SC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_CC */ #ifndef __MAC_QCU_ONESHOT_ARM_CC_MACRO__ #define __MAC_QCU_ONESHOT_ARM_CC_MACRO__ /* macros for field CLEAR */ #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__SHIFT 0 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WIDTH 10 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MASK 0x000003ffU #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WRITE(src) \ ((u_int32_t)(src)\ & 0x000003ffU) #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) #define MAC_QCU_ONESHOT_ARM_CC__TYPE u_int32_t #define MAC_QCU_ONESHOT_ARM_CC__READ 0x000003ffU #define MAC_QCU_ONESHOT_ARM_CC__WRITE 0x000003ffU #endif /* __MAC_QCU_ONESHOT_ARM_CC_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_CC */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_CC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_MISC */ #ifndef __MAC_QCU_MISC_MACRO__ #define __MAC_QCU_MISC_MACRO__ /* macros for field FSP */ #define MAC_QCU_MISC__FSP__SHIFT 0 #define MAC_QCU_MISC__FSP__WIDTH 4 #define MAC_QCU_MISC__FSP__MASK 0x0000000fU #define MAC_QCU_MISC__FSP__READ(src) (u_int32_t)(src) & 0x0000000fU #define MAC_QCU_MISC__FSP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) #define MAC_QCU_MISC__FSP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_QCU_MISC__FSP__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) /* macros for field ONESHOT_EN */ #define MAC_QCU_MISC__ONESHOT_EN__SHIFT 4 #define MAC_QCU_MISC__ONESHOT_EN__WIDTH 1 #define MAC_QCU_MISC__ONESHOT_EN__MASK 0x00000010U #define MAC_QCU_MISC__ONESHOT_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_QCU_MISC__ONESHOT_EN__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_QCU_MISC__ONESHOT_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_QCU_MISC__ONESHOT_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_QCU_MISC__ONESHOT_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field CBR_EXP_INC_DIS_NOFR */ #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SHIFT 5 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WIDTH 1 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MASK 0x00000020U #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field CBR_EXP_INC_DIS_NOBCNFR */ #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SHIFT 6 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WIDTH 1 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MASK 0x00000040U #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field IS_BCN */ #define MAC_QCU_MISC__IS_BCN__SHIFT 7 #define MAC_QCU_MISC__IS_BCN__WIDTH 1 #define MAC_QCU_MISC__IS_BCN__MASK 0x00000080U #define MAC_QCU_MISC__IS_BCN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) #define MAC_QCU_MISC__IS_BCN__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_QCU_MISC__IS_BCN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_QCU_MISC__IS_BCN__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_QCU_MISC__IS_BCN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field CBR_EXP_INC_LIMIT */ #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SHIFT 8 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WIDTH 1 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MASK 0x00000100U #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field TXE_CLR_ON_CBR_END */ #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SHIFT 9 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WIDTH 1 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MASK 0x00000200U #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field MMR_CBR_EXP_CNT_CLR_EN */ #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SHIFT 10 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WIDTH 1 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MASK 0x00000400U #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field FR_ABORT_REQ_EN */ #define MAC_QCU_MISC__FR_ABORT_REQ_EN__SHIFT 11 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__WIDTH 1 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__MASK 0x00000800U #define MAC_QCU_MISC__FR_ABORT_REQ_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_QCU_MISC__FR_ABORT_REQ_EN__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_QCU_MISC__FR_ABORT_REQ_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_QCU_MISC__FR_ABORT_REQ_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_QCU_MISC__FR_ABORT_REQ_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) #define MAC_QCU_MISC__TYPE u_int32_t #define MAC_QCU_MISC__READ 0x00000fffU #define MAC_QCU_MISC__WRITE 0x00000fffU #endif /* __MAC_QCU_MISC_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_MISC */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_MISC__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_QCU_CNT */ #ifndef __MAC_QCU_CNT_MACRO__ #define __MAC_QCU_CNT_MACRO__ /* macros for field FR_PEND */ #define MAC_QCU_CNT__FR_PEND__SHIFT 0 #define MAC_QCU_CNT__FR_PEND__WIDTH 2 #define MAC_QCU_CNT__FR_PEND__MASK 0x00000003U #define MAC_QCU_CNT__FR_PEND__READ(src) (u_int32_t)(src) & 0x00000003U /* macros for field CBR_EXP */ #define MAC_QCU_CNT__CBR_EXP__SHIFT 8 #define MAC_QCU_CNT__CBR_EXP__WIDTH 8 #define MAC_QCU_CNT__CBR_EXP__MASK 0x0000ff00U #define MAC_QCU_CNT__CBR_EXP__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define MAC_QCU_CNT__TYPE u_int32_t #define MAC_QCU_CNT__READ 0x0000ff03U #endif /* __MAC_QCU_CNT_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_CNT */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_CNT__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME_SHDN */ #ifndef __MAC_QCU_RDYTIME_SHDN_MACRO__ #define __MAC_QCU_RDYTIME_SHDN_MACRO__ /* macros for field SHUTDOWN */ #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__SHIFT 0 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WIDTH 10 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MASK 0x000003ffU #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__READ(src) \ (u_int32_t)(src)\ & 0x000003ffU #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WRITE(src) \ ((u_int32_t)(src)\ & 0x000003ffU) #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) #define MAC_QCU_RDYTIME_SHDN__TYPE u_int32_t #define MAC_QCU_RDYTIME_SHDN__READ 0x000003ffU #define MAC_QCU_RDYTIME_SHDN__WRITE 0x000003ffU #define MAC_QCU_RDYTIME_SHDN__WOCLR 0x000003ffU #endif /* __MAC_QCU_RDYTIME_SHDN_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME_SHDN */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME_SHDN__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_QCU_DESC_CRC_CHK */ #ifndef __MAC_QCU_DESC_CRC_CHK_MACRO__ #define __MAC_QCU_DESC_CRC_CHK_MACRO__ /* macros for field EN */ #define MAC_QCU_DESC_CRC_CHK__EN__SHIFT 0 #define MAC_QCU_DESC_CRC_CHK__EN__WIDTH 1 #define MAC_QCU_DESC_CRC_CHK__EN__MASK 0x00000001U #define MAC_QCU_DESC_CRC_CHK__EN__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_QCU_DESC_CRC_CHK__EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_QCU_DESC_CRC_CHK__EN__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_QCU_DESC_CRC_CHK__EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_QCU_DESC_CRC_CHK__EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) #define MAC_QCU_DESC_CRC_CHK__TYPE u_int32_t #define MAC_QCU_DESC_CRC_CHK__READ 0x00000001U #define MAC_QCU_DESC_CRC_CHK__WRITE 0x00000001U #endif /* __MAC_QCU_DESC_CRC_CHK_MACRO__ */ /* macros for mac_qcu_reg_map.MAC_QCU_DESC_CRC_CHK */ #define INST_MAC_QCU_REG_MAP__MAC_QCU_DESC_CRC_CHK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_QCUMASK */ #ifndef __MAC_DCU_QCUMASK_MACRO__ #define __MAC_DCU_QCUMASK_MACRO__ /* macros for field DATA */ #define MAC_DCU_QCUMASK__DATA__SHIFT 0 #define MAC_DCU_QCUMASK__DATA__WIDTH 10 #define MAC_DCU_QCUMASK__DATA__MASK 0x000003ffU #define MAC_DCU_QCUMASK__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_DCU_QCUMASK__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_DCU_QCUMASK__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) #define MAC_DCU_QCUMASK__TYPE u_int32_t #define MAC_DCU_QCUMASK__READ 0x000003ffU #define MAC_DCU_QCUMASK__WRITE 0x000003ffU #endif /* __MAC_DCU_QCUMASK_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_QCUMASK */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_QCUMASK__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SIFS */ #ifndef __MAC_DCU_GBL_IFS_SIFS_MACRO__ #define __MAC_DCU_GBL_IFS_SIFS_MACRO__ /* macros for field DURATION */ #define MAC_DCU_GBL_IFS_SIFS__DURATION__SHIFT 0 #define MAC_DCU_GBL_IFS_SIFS__DURATION__WIDTH 16 #define MAC_DCU_GBL_IFS_SIFS__DURATION__MASK 0x0000ffffU #define MAC_DCU_GBL_IFS_SIFS__DURATION__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DCU_GBL_IFS_SIFS__DURATION__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DCU_GBL_IFS_SIFS__DURATION__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_DCU_GBL_IFS_SIFS__TYPE u_int32_t #define MAC_DCU_GBL_IFS_SIFS__READ 0x0000ffffU #define MAC_DCU_GBL_IFS_SIFS__WRITE 0x0000ffffU #endif /* __MAC_DCU_GBL_IFS_SIFS_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SIFS */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SIFS__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DCU_TXFILTER_DCU0_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU0_31_0__READ 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_31_0__WRITE 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU8_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU8_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU8_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU8_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_LCL_IFS */ #ifndef __MAC_DCU_LCL_IFS_MACRO__ #define __MAC_DCU_LCL_IFS_MACRO__ /* macros for field CW_MIN */ #define MAC_DCU_LCL_IFS__CW_MIN__SHIFT 0 #define MAC_DCU_LCL_IFS__CW_MIN__WIDTH 10 #define MAC_DCU_LCL_IFS__CW_MIN__MASK 0x000003ffU #define MAC_DCU_LCL_IFS__CW_MIN__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_DCU_LCL_IFS__CW_MIN__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_DCU_LCL_IFS__CW_MIN__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) /* macros for field CW_MAX */ #define MAC_DCU_LCL_IFS__CW_MAX__SHIFT 10 #define MAC_DCU_LCL_IFS__CW_MAX__WIDTH 10 #define MAC_DCU_LCL_IFS__CW_MAX__MASK 0x000ffc00U #define MAC_DCU_LCL_IFS__CW_MAX__READ(src) \ (((u_int32_t)(src)\ & 0x000ffc00U) >> 10) #define MAC_DCU_LCL_IFS__CW_MAX__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x000ffc00U) #define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000ffc00U) | (((u_int32_t)(src) <<\ 10) & 0x000ffc00U) #define MAC_DCU_LCL_IFS__CW_MAX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x000ffc00U))) /* macros for field AIFS */ #define MAC_DCU_LCL_IFS__AIFS__SHIFT 20 #define MAC_DCU_LCL_IFS__AIFS__WIDTH 8 #define MAC_DCU_LCL_IFS__AIFS__MASK 0x0ff00000U #define MAC_DCU_LCL_IFS__AIFS__READ(src) \ (((u_int32_t)(src)\ & 0x0ff00000U) >> 20) #define MAC_DCU_LCL_IFS__AIFS__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x0ff00000U) #define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0ff00000U) | (((u_int32_t)(src) <<\ 20) & 0x0ff00000U) #define MAC_DCU_LCL_IFS__AIFS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x0ff00000U))) /* macros for field LONG_AIFS */ #define MAC_DCU_LCL_IFS__LONG_AIFS__SHIFT 28 #define MAC_DCU_LCL_IFS__LONG_AIFS__WIDTH 1 #define MAC_DCU_LCL_IFS__LONG_AIFS__MASK 0x10000000U #define MAC_DCU_LCL_IFS__LONG_AIFS__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define MAC_DCU_LCL_IFS__LONG_AIFS__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define MAC_DCU_LCL_IFS__LONG_AIFS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define MAC_DCU_LCL_IFS__LONG_AIFS__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define MAC_DCU_LCL_IFS__LONG_AIFS__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) #define MAC_DCU_LCL_IFS__TYPE u_int32_t #define MAC_DCU_LCL_IFS__READ 0x1fffffffU #define MAC_DCU_LCL_IFS__WRITE 0x1fffffffU #endif /* __MAC_DCU_LCL_IFS_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_LCL_IFS */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_LCL_IFS__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SLOT */ #ifndef __MAC_DCU_GBL_IFS_SLOT_MACRO__ #define __MAC_DCU_GBL_IFS_SLOT_MACRO__ /* macros for field DURATION */ #define MAC_DCU_GBL_IFS_SLOT__DURATION__SHIFT 0 #define MAC_DCU_GBL_IFS_SLOT__DURATION__WIDTH 16 #define MAC_DCU_GBL_IFS_SLOT__DURATION__MASK 0x0000ffffU #define MAC_DCU_GBL_IFS_SLOT__DURATION__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DCU_GBL_IFS_SLOT__DURATION__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DCU_GBL_IFS_SLOT__DURATION__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_DCU_GBL_IFS_SLOT__TYPE u_int32_t #define MAC_DCU_GBL_IFS_SLOT__READ 0x0000ffffU #define MAC_DCU_GBL_IFS_SLOT__WRITE 0x0000ffffU #endif /* __MAC_DCU_GBL_IFS_SLOT_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SLOT */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SLOT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DCU_TXFILTER_DCU0_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU0_63_32__READ 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_63_32__WRITE 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU8_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU8_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU8_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU8_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_RETRY_LIMIT */ #ifndef __MAC_DCU_RETRY_LIMIT_MACRO__ #define __MAC_DCU_RETRY_LIMIT_MACRO__ /* macros for field FRFL */ #define MAC_DCU_RETRY_LIMIT__FRFL__SHIFT 0 #define MAC_DCU_RETRY_LIMIT__FRFL__WIDTH 4 #define MAC_DCU_RETRY_LIMIT__FRFL__MASK 0x0000000fU #define MAC_DCU_RETRY_LIMIT__FRFL__READ(src) (u_int32_t)(src) & 0x0000000fU #define MAC_DCU_RETRY_LIMIT__FRFL__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) #define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_DCU_RETRY_LIMIT__FRFL__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000000fU))) /* macros for field SRFL */ #define MAC_DCU_RETRY_LIMIT__SRFL__SHIFT 8 #define MAC_DCU_RETRY_LIMIT__SRFL__WIDTH 6 #define MAC_DCU_RETRY_LIMIT__SRFL__MASK 0x00003f00U #define MAC_DCU_RETRY_LIMIT__SRFL__READ(src) \ (((u_int32_t)(src)\ & 0x00003f00U) >> 8) #define MAC_DCU_RETRY_LIMIT__SRFL__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00003f00U) #define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00003f00U) | (((u_int32_t)(src) <<\ 8) & 0x00003f00U) #define MAC_DCU_RETRY_LIMIT__SRFL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00003f00U))) /* macros for field SDFL */ #define MAC_DCU_RETRY_LIMIT__SDFL__SHIFT 14 #define MAC_DCU_RETRY_LIMIT__SDFL__WIDTH 6 #define MAC_DCU_RETRY_LIMIT__SDFL__MASK 0x000fc000U #define MAC_DCU_RETRY_LIMIT__SDFL__READ(src) \ (((u_int32_t)(src)\ & 0x000fc000U) >> 14) #define MAC_DCU_RETRY_LIMIT__SDFL__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x000fc000U) #define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000fc000U) | (((u_int32_t)(src) <<\ 14) & 0x000fc000U) #define MAC_DCU_RETRY_LIMIT__SDFL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x000fc000U))) #define MAC_DCU_RETRY_LIMIT__TYPE u_int32_t #define MAC_DCU_RETRY_LIMIT__READ 0x000fff0fU #define MAC_DCU_RETRY_LIMIT__WRITE 0x000fff0fU #endif /* __MAC_DCU_RETRY_LIMIT_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_RETRY_LIMIT */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_RETRY_LIMIT__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_EIFS */ #ifndef __MAC_DCU_GBL_IFS_EIFS_MACRO__ #define __MAC_DCU_GBL_IFS_EIFS_MACRO__ /* macros for field DURATION */ #define MAC_DCU_GBL_IFS_EIFS__DURATION__SHIFT 0 #define MAC_DCU_GBL_IFS_EIFS__DURATION__WIDTH 16 #define MAC_DCU_GBL_IFS_EIFS__DURATION__MASK 0x0000ffffU #define MAC_DCU_GBL_IFS_EIFS__DURATION__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_DCU_GBL_IFS_EIFS__DURATION__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DCU_GBL_IFS_EIFS__DURATION__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_DCU_GBL_IFS_EIFS__TYPE u_int32_t #define MAC_DCU_GBL_IFS_EIFS__READ 0x0000ffffU #define MAC_DCU_GBL_IFS_EIFS__WRITE 0x0000ffffU #endif /* __MAC_DCU_GBL_IFS_EIFS_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_EIFS */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_EIFS__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DCU_TXFILTER_DCU0_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU0_95_64__READ 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_95_64__WRITE 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU8_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU8_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU8_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU8_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_CHANNEL_TIME */ #ifndef __MAC_DCU_CHANNEL_TIME_MACRO__ #define __MAC_DCU_CHANNEL_TIME_MACRO__ /* macros for field DURATION */ #define MAC_DCU_CHANNEL_TIME__DURATION__SHIFT 0 #define MAC_DCU_CHANNEL_TIME__DURATION__WIDTH 20 #define MAC_DCU_CHANNEL_TIME__DURATION__MASK 0x000fffffU #define MAC_DCU_CHANNEL_TIME__DURATION__READ(src) \ (u_int32_t)(src)\ & 0x000fffffU #define MAC_DCU_CHANNEL_TIME__DURATION__WRITE(src) \ ((u_int32_t)(src)\ & 0x000fffffU) #define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000fffffU) | ((u_int32_t)(src) &\ 0x000fffffU) #define MAC_DCU_CHANNEL_TIME__DURATION__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000fffffU))) /* macros for field ENABLE */ #define MAC_DCU_CHANNEL_TIME__ENABLE__SHIFT 20 #define MAC_DCU_CHANNEL_TIME__ENABLE__WIDTH 1 #define MAC_DCU_CHANNEL_TIME__ENABLE__MASK 0x00100000U #define MAC_DCU_CHANNEL_TIME__ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_DCU_CHANNEL_TIME__ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_DCU_CHANNEL_TIME__ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_DCU_CHANNEL_TIME__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_DCU_CHANNEL_TIME__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) #define MAC_DCU_CHANNEL_TIME__TYPE u_int32_t #define MAC_DCU_CHANNEL_TIME__READ 0x001fffffU #define MAC_DCU_CHANNEL_TIME__WRITE 0x001fffffU #endif /* __MAC_DCU_CHANNEL_TIME_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_CHANNEL_TIME */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_CHANNEL_TIME__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_MISC */ #ifndef __MAC_DCU_GBL_IFS_MISC_MACRO__ #define __MAC_DCU_GBL_IFS_MISC_MACRO__ /* macros for field LFSR_SLICE_SEL */ #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__SHIFT 0 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WIDTH 3 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MASK 0x00000007U #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__READ(src) \ (u_int32_t)(src)\ & 0x00000007U #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000007U) #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000007U) | ((u_int32_t)(src) &\ 0x00000007U) #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000007U))) /* macros for field TURBO_MODE */ #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SHIFT 3 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WIDTH 1 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MASK 0x00000008U #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field SIFS_DUR_USEC */ #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__SHIFT 4 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WIDTH 6 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MASK 0x000003f0U #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__READ(src) \ (((u_int32_t)(src)\ & 0x000003f0U) >> 4) #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x000003f0U) #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003f0U) | (((u_int32_t)(src) <<\ 4) & 0x000003f0U) #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x000003f0U))) /* macros for field ARB_DLY */ #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__SHIFT 20 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WIDTH 2 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MASK 0x00300000U #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__READ(src) \ (((u_int32_t)(src)\ & 0x00300000U) >> 20) #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00300000U) #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00300000U) | (((u_int32_t)(src) <<\ 20) & 0x00300000U) #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00300000U))) /* macros for field SIFS_RST_UNCOND */ #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SHIFT 22 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WIDTH 1 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MASK 0x00400000U #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field AIFS_RST_UNCOND */ #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SHIFT 23 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WIDTH 1 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MASK 0x00800000U #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field LFSR_SLICE_RANDOM_DIS */ #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SHIFT 24 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WIDTH 1 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MASK 0x01000000U #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field CHAN_SLOT_WIN_DUR */ #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__SHIFT 25 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WIDTH 2 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MASK 0x06000000U #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__READ(src) \ (((u_int32_t)(src)\ & 0x06000000U) >> 25) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x06000000U) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x06000000U) | (((u_int32_t)(src) <<\ 25) & 0x06000000U) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x06000000U))) /* macros for field CHAN_SLOT_ALWAYS */ #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SHIFT 27 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WIDTH 1 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MASK 0x08000000U #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field IGNORE_BACKOFF */ #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SHIFT 28 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WIDTH 1 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MASK 0x10000000U #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field SLOT_COUNT_RST_UNCOND */ #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SHIFT 29 #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WIDTH 1 #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MASK 0x20000000U #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) #define MAC_DCU_GBL_IFS_MISC__TYPE u_int32_t #define MAC_DCU_GBL_IFS_MISC__READ 0x3ff003ffU #define MAC_DCU_GBL_IFS_MISC__WRITE 0x3ff003ffU #endif /* __MAC_DCU_GBL_IFS_MISC_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_MISC */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_MISC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DCU_TXFILTER_DCU0_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU0_127_96__READ 0xffffffffU #define MAC_DCU_TXFILTER_DCU0_127_96__WRITE 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU8_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU8_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU8_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU8_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU8_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_MISC */ #ifndef __MAC_DCU_MISC_MACRO__ #define __MAC_DCU_MISC_MACRO__ /* macros for field BKOFF_THRESH */ #define MAC_DCU_MISC__BKOFF_THRESH__SHIFT 0 #define MAC_DCU_MISC__BKOFF_THRESH__WIDTH 6 #define MAC_DCU_MISC__BKOFF_THRESH__MASK 0x0000003fU #define MAC_DCU_MISC__BKOFF_THRESH__READ(src) (u_int32_t)(src) & 0x0000003fU #define MAC_DCU_MISC__BKOFF_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) #define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000003fU) | ((u_int32_t)(src) &\ 0x0000003fU) #define MAC_DCU_MISC__BKOFF_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000003fU))) /* macros for field SFC_RST_AT_TS_END_EN */ #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SHIFT 6 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WIDTH 1 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MASK 0x00000040U #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field CW_RST_AT_TS_END_DIS */ #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SHIFT 7 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WIDTH 1 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MASK 0x00000080U #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field FRAG_BURST_WAIT_QCU_EN */ #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SHIFT 8 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WIDTH 1 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MASK 0x00000100U #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field FRAG_BURST_BKOFF_EN */ #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SHIFT 9 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WIDTH 1 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MASK 0x00000200U #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field HCF_POLL_EN */ #define MAC_DCU_MISC__HCF_POLL_EN__SHIFT 11 #define MAC_DCU_MISC__HCF_POLL_EN__WIDTH 1 #define MAC_DCU_MISC__HCF_POLL_EN__MASK 0x00000800U #define MAC_DCU_MISC__HCF_POLL_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_DCU_MISC__HCF_POLL_EN__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_DCU_MISC__HCF_POLL_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_DCU_MISC__HCF_POLL_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_DCU_MISC__HCF_POLL_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field BKOFF_PF */ #define MAC_DCU_MISC__BKOFF_PF__SHIFT 12 #define MAC_DCU_MISC__BKOFF_PF__WIDTH 1 #define MAC_DCU_MISC__BKOFF_PF__MASK 0x00001000U #define MAC_DCU_MISC__BKOFF_PF__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_DCU_MISC__BKOFF_PF__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_DCU_MISC__BKOFF_PF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_DCU_MISC__BKOFF_PF__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_DCU_MISC__BKOFF_PF__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field VIRT_COLL_POLICY */ #define MAC_DCU_MISC__VIRT_COLL_POLICY__SHIFT 14 #define MAC_DCU_MISC__VIRT_COLL_POLICY__WIDTH 2 #define MAC_DCU_MISC__VIRT_COLL_POLICY__MASK 0x0000c000U #define MAC_DCU_MISC__VIRT_COLL_POLICY__READ(src) \ (((u_int32_t)(src)\ & 0x0000c000U) >> 14) #define MAC_DCU_MISC__VIRT_COLL_POLICY__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x0000c000U) #define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000c000U) | (((u_int32_t)(src) <<\ 14) & 0x0000c000U) #define MAC_DCU_MISC__VIRT_COLL_POLICY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x0000c000U))) /* macros for field IS_BCN */ #define MAC_DCU_MISC__IS_BCN__SHIFT 16 #define MAC_DCU_MISC__IS_BCN__WIDTH 1 #define MAC_DCU_MISC__IS_BCN__MASK 0x00010000U #define MAC_DCU_MISC__IS_BCN__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_DCU_MISC__IS_BCN__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_DCU_MISC__IS_BCN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_DCU_MISC__IS_BCN__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_DCU_MISC__IS_BCN__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field ARB_LOCKOUT_IF_EN */ #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SHIFT 17 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WIDTH 1 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MASK 0x00020000U #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field LOCKOUT_GBL_EN */ #define MAC_DCU_MISC__LOCKOUT_GBL_EN__SHIFT 18 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__WIDTH 1 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__MASK 0x00040000U #define MAC_DCU_MISC__LOCKOUT_GBL_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_DCU_MISC__LOCKOUT_GBL_EN__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_DCU_MISC__LOCKOUT_GBL_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_DCU_MISC__LOCKOUT_GBL_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_DCU_MISC__LOCKOUT_GBL_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field LOCKOUT_IGNORE */ #define MAC_DCU_MISC__LOCKOUT_IGNORE__SHIFT 19 #define MAC_DCU_MISC__LOCKOUT_IGNORE__WIDTH 1 #define MAC_DCU_MISC__LOCKOUT_IGNORE__MASK 0x00080000U #define MAC_DCU_MISC__LOCKOUT_IGNORE__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_DCU_MISC__LOCKOUT_IGNORE__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_DCU_MISC__LOCKOUT_IGNORE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_DCU_MISC__LOCKOUT_IGNORE__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_DCU_MISC__LOCKOUT_IGNORE__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field SEQNUM_FREEZE */ #define MAC_DCU_MISC__SEQNUM_FREEZE__SHIFT 20 #define MAC_DCU_MISC__SEQNUM_FREEZE__WIDTH 1 #define MAC_DCU_MISC__SEQNUM_FREEZE__MASK 0x00100000U #define MAC_DCU_MISC__SEQNUM_FREEZE__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_DCU_MISC__SEQNUM_FREEZE__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_DCU_MISC__SEQNUM_FREEZE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_DCU_MISC__SEQNUM_FREEZE__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_DCU_MISC__SEQNUM_FREEZE__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field POST_BKOFF_SKIP */ #define MAC_DCU_MISC__POST_BKOFF_SKIP__SHIFT 21 #define MAC_DCU_MISC__POST_BKOFF_SKIP__WIDTH 1 #define MAC_DCU_MISC__POST_BKOFF_SKIP__MASK 0x00200000U #define MAC_DCU_MISC__POST_BKOFF_SKIP__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_DCU_MISC__POST_BKOFF_SKIP__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_DCU_MISC__POST_BKOFF_SKIP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_DCU_MISC__POST_BKOFF_SKIP__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_DCU_MISC__POST_BKOFF_SKIP__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field VIRT_COLL_CW_INC_EN */ #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SHIFT 22 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WIDTH 1 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MASK 0x00400000U #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field RETRY_ON_BLOWN_IFS_EN */ #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SHIFT 23 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WIDTH 1 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MASK 0x00800000U #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field SIFS_BURST_CHAN_BUSY_IGNORE */ #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SHIFT 24 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WIDTH 1 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MASK 0x01000000U #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) #define MAC_DCU_MISC__TYPE u_int32_t #define MAC_DCU_MISC__READ 0x01ffdbffU #define MAC_DCU_MISC__WRITE 0x01ffdbffU #endif /* __MAC_DCU_MISC_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_MISC */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_MISC__NUM 10 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU1_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU1_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU1_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU1_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU9_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU9_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU9_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU9_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_SEQ */ #ifndef __MAC_DCU_SEQ_MACRO__ #define __MAC_DCU_SEQ_MACRO__ /* macros for field NUM */ #define MAC_DCU_SEQ__NUM__SHIFT 0 #define MAC_DCU_SEQ__NUM__WIDTH 32 #define MAC_DCU_SEQ__NUM__MASK 0xffffffffU #define MAC_DCU_SEQ__NUM__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DCU_SEQ__NUM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DCU_SEQ__NUM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) #define MAC_DCU_SEQ__TYPE u_int32_t #define MAC_DCU_SEQ__READ 0xffffffffU #define MAC_DCU_SEQ__WRITE 0xffffffffU #endif /* __MAC_DCU_SEQ_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_SEQ */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_SEQ__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU1_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU1_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU1_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU1_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU9_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU9_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU9_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU9_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU1_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU1_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU1_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU1_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU9_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU9_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU9_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU9_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU1_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU1_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU1_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU1_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU1_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU9_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU9_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU9_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU9_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU9_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU2_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU2_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU2_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU2_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_PAUSE */ #ifndef __MAC_DCU_PAUSE_MACRO__ #define __MAC_DCU_PAUSE_MACRO__ /* macros for field REQUEST */ #define MAC_DCU_PAUSE__REQUEST__SHIFT 0 #define MAC_DCU_PAUSE__REQUEST__WIDTH 10 #define MAC_DCU_PAUSE__REQUEST__MASK 0x000003ffU #define MAC_DCU_PAUSE__REQUEST__READ(src) (u_int32_t)(src) & 0x000003ffU #define MAC_DCU_PAUSE__REQUEST__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define MAC_DCU_PAUSE__REQUEST__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) /* macros for field STATUS */ #define MAC_DCU_PAUSE__STATUS__SHIFT 16 #define MAC_DCU_PAUSE__STATUS__WIDTH 1 #define MAC_DCU_PAUSE__STATUS__MASK 0x00010000U #define MAC_DCU_PAUSE__STATUS__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_DCU_PAUSE__STATUS__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_DCU_PAUSE__STATUS__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field SPARE */ #define MAC_DCU_PAUSE__SPARE__SHIFT 17 #define MAC_DCU_PAUSE__SPARE__WIDTH 4 #define MAC_DCU_PAUSE__SPARE__MASK 0x001e0000U #define MAC_DCU_PAUSE__SPARE__READ(src) \ (((u_int32_t)(src)\ & 0x001e0000U) >> 17) #define MAC_DCU_PAUSE__SPARE__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x001e0000U) #define MAC_DCU_PAUSE__SPARE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x001e0000U) | (((u_int32_t)(src) <<\ 17) & 0x001e0000U) #define MAC_DCU_PAUSE__SPARE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x001e0000U))) #define MAC_DCU_PAUSE__TYPE u_int32_t #define MAC_DCU_PAUSE__READ 0x001f03ffU #define MAC_DCU_PAUSE__WRITE 0x001f03ffU #endif /* __MAC_DCU_PAUSE_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_PAUSE */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_PAUSE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU2_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU2_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU2_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU2_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_WOW_KACFG */ #ifndef __MAC_DCU_WOW_KACFG_MACRO__ #define __MAC_DCU_WOW_KACFG_MACRO__ /* macros for field TX_EN */ #define MAC_DCU_WOW_KACFG__TX_EN__SHIFT 0 #define MAC_DCU_WOW_KACFG__TX_EN__WIDTH 1 #define MAC_DCU_WOW_KACFG__TX_EN__MASK 0x00000001U #define MAC_DCU_WOW_KACFG__TX_EN__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_DCU_WOW_KACFG__TX_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_DCU_WOW_KACFG__TX_EN__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_DCU_WOW_KACFG__TX_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_DCU_WOW_KACFG__TX_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field TIM_EN */ #define MAC_DCU_WOW_KACFG__TIM_EN__SHIFT 1 #define MAC_DCU_WOW_KACFG__TIM_EN__WIDTH 1 #define MAC_DCU_WOW_KACFG__TIM_EN__MASK 0x00000002U #define MAC_DCU_WOW_KACFG__TIM_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_DCU_WOW_KACFG__TIM_EN__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_DCU_WOW_KACFG__TIM_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_DCU_WOW_KACFG__TIM_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_DCU_WOW_KACFG__TIM_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field BCN_CNT */ #define MAC_DCU_WOW_KACFG__BCN_CNT__SHIFT 4 #define MAC_DCU_WOW_KACFG__BCN_CNT__WIDTH 8 #define MAC_DCU_WOW_KACFG__BCN_CNT__MASK 0x00000ff0U #define MAC_DCU_WOW_KACFG__BCN_CNT__READ(src) \ (((u_int32_t)(src)\ & 0x00000ff0U) >> 4) #define MAC_DCU_WOW_KACFG__BCN_CNT__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000ff0U) #define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000ff0U) | (((u_int32_t)(src) <<\ 4) & 0x00000ff0U) #define MAC_DCU_WOW_KACFG__BCN_CNT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000ff0U))) /* macros for field RX_TIMEOUT_CNT */ #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__SHIFT 12 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WIDTH 12 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MASK 0x00fff000U #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__READ(src) \ (((u_int32_t)(src)\ & 0x00fff000U) >> 12) #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00fff000U) #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00fff000U) | (((u_int32_t)(src) <<\ 12) & 0x00fff000U) #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00fff000U))) #define MAC_DCU_WOW_KACFG__TYPE u_int32_t #define MAC_DCU_WOW_KACFG__READ 0x00fffff3U #define MAC_DCU_WOW_KACFG__WRITE 0x00fffff3U #endif /* __MAC_DCU_WOW_KACFG_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_WOW_KACFG */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_WOW_KACFG__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU2_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU2_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU2_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU2_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXSLOT */ #ifndef __MAC_DCU_TXSLOT_MACRO__ #define __MAC_DCU_TXSLOT_MACRO__ /* macros for field MASK */ #define MAC_DCU_TXSLOT__MASK__SHIFT 0 #define MAC_DCU_TXSLOT__MASK__WIDTH 16 #define MAC_DCU_TXSLOT__MASK__MASK 0x0000ffffU #define MAC_DCU_TXSLOT__MASK__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_DCU_TXSLOT__MASK__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_DCU_TXSLOT__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_DCU_TXSLOT__TYPE u_int32_t #define MAC_DCU_TXSLOT__READ 0x0000ffffU #define MAC_DCU_TXSLOT__WRITE 0x0000ffffU #endif /* __MAC_DCU_TXSLOT_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXSLOT */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXSLOT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU2_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU2_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU2_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU2_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU2_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU3_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU3_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU3_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU3_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU3_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU3_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU3_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU3_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU3_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU3_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU3_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU3_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU3_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU3_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU3_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU3_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU3_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU4_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU4_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU4_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU4_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_CLEAR */ #ifndef __MAC_DCU_TXFILTER_CLEAR_MACRO__ #define __MAC_DCU_TXFILTER_CLEAR_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_CLEAR__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_CLEAR__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_CLEAR__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_CLEAR__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DCU_TXFILTER_CLEAR__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DCU_TXFILTER_CLEAR__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DCU_TXFILTER_CLEAR__TYPE u_int32_t #define MAC_DCU_TXFILTER_CLEAR__READ 0xffffffffU #define MAC_DCU_TXFILTER_CLEAR__WRITE 0xffffffffU #endif /* __MAC_DCU_TXFILTER_CLEAR_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_CLEAR */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_CLEAR__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU4_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU4_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU4_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU4_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_SET */ #ifndef __MAC_DCU_TXFILTER_SET_MACRO__ #define __MAC_DCU_TXFILTER_SET_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_SET__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_SET__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_SET__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_SET__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_DCU_TXFILTER_SET__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_DCU_TXFILTER_SET__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_DCU_TXFILTER_SET__TYPE u_int32_t #define MAC_DCU_TXFILTER_SET__READ 0xffffffffU #define MAC_DCU_TXFILTER_SET__WRITE 0xffffffffU #endif /* __MAC_DCU_TXFILTER_SET_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_SET */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_SET__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU4_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU4_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU4_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU4_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU4_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU4_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU4_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU4_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU4_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU5_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU5_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU5_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU5_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU5_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU5_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU5_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU5_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU5_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU5_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU5_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU5_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU5_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU5_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU5_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU5_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU5_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU6_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU6_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU6_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU6_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU6_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU6_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU6_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU6_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU6_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU6_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU6_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU6_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU6_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU6_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU6_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU6_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU6_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_31_0 */ #ifndef __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ #define __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU7_31_0__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU7_31_0__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU7_31_0__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_31_0__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_31_0__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU7_31_0__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_31_0 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_31_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_63_32 */ #ifndef __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ #define __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU7_63_32__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU7_63_32__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU7_63_32__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_63_32__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_63_32__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU7_63_32__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_63_32 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_63_32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_95_64 */ #ifndef __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ #define __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU7_95_64__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU7_95_64__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU7_95_64__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_95_64__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_95_64__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU7_95_64__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_95_64 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_95_64__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_127_96 */ #ifndef __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ #define __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ /* macros for field DATA */ #define MAC_DCU_TXFILTER_DCU7_127_96__DATA__SHIFT 0 #define MAC_DCU_TXFILTER_DCU7_127_96__DATA__WIDTH 32 #define MAC_DCU_TXFILTER_DCU7_127_96__DATA__MASK 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_127_96__DATA__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_DCU_TXFILTER_DCU7_127_96__TYPE u_int32_t #define MAC_DCU_TXFILTER_DCU7_127_96__READ 0xffffffffU #endif /* __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_127_96 */ #define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_127_96__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_SLEEP_STATUS */ #ifndef __MAC_SLEEP_STATUS_MACRO__ #define __MAC_SLEEP_STATUS_MACRO__ /* macros for field DATA */ #define MAC_SLEEP_STATUS__DATA__SHIFT 0 #define MAC_SLEEP_STATUS__DATA__WIDTH 32 #define MAC_SLEEP_STATUS__DATA__MASK 0xffffffffU #define MAC_SLEEP_STATUS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_SLEEP_STATUS__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_SLEEP_STATUS__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_SLEEP_STATUS__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_SLEEP_STATUS__TYPE u_int32_t #define MAC_SLEEP_STATUS__READ 0xffffffffU #define MAC_SLEEP_STATUS__WRITE 0xffffffffU #endif /* __MAC_SLEEP_STATUS_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_SLEEP_STATUS */ #define INST_MAC_DCU_REG_MAP__MAC_SLEEP_STATUS__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_LED_CONFIG */ #ifndef __MAC_LED_CONFIG_MACRO__ #define __MAC_LED_CONFIG_MACRO__ /* macros for field DATA */ #define MAC_LED_CONFIG__DATA__SHIFT 0 #define MAC_LED_CONFIG__DATA__WIDTH 32 #define MAC_LED_CONFIG__DATA__MASK 0xffffffffU #define MAC_LED_CONFIG__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_LED_CONFIG__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_LED_CONFIG__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_LED_CONFIG__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_LED_CONFIG__TYPE u_int32_t #define MAC_LED_CONFIG__READ 0xffffffffU #define MAC_LED_CONFIG__WRITE 0xffffffffU #endif /* __MAC_LED_CONFIG_MACRO__ */ /* macros for mac_dcu_reg_map.MAC_LED_CONFIG */ #define INST_MAC_DCU_REG_MAP__MAC_LED_CONFIG__NUM 1 /* macros for BlueprintGlobalNameSpace::RESET_CONTROL */ #ifndef __RESET_CONTROL_MACRO__ #define __RESET_CONTROL_MACRO__ /* macros for field MAC_WARM_RST */ #define RESET_CONTROL__MAC_WARM_RST__SHIFT 0 #define RESET_CONTROL__MAC_WARM_RST__WIDTH 1 #define RESET_CONTROL__MAC_WARM_RST__MASK 0x00000001U #define RESET_CONTROL__MAC_WARM_RST__READ(src) (u_int32_t)(src) & 0x00000001U #define RESET_CONTROL__MAC_WARM_RST__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define RESET_CONTROL__MAC_WARM_RST__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define RESET_CONTROL__MAC_WARM_RST__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RESET_CONTROL__MAC_WARM_RST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field MAC_COLD_RST */ #define RESET_CONTROL__MAC_COLD_RST__SHIFT 1 #define RESET_CONTROL__MAC_COLD_RST__WIDTH 1 #define RESET_CONTROL__MAC_COLD_RST__MASK 0x00000002U #define RESET_CONTROL__MAC_COLD_RST__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define RESET_CONTROL__MAC_COLD_RST__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define RESET_CONTROL__MAC_COLD_RST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define RESET_CONTROL__MAC_COLD_RST__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define RESET_CONTROL__MAC_COLD_RST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field WARM_RST */ #define RESET_CONTROL__WARM_RST__SHIFT 2 #define RESET_CONTROL__WARM_RST__WIDTH 1 #define RESET_CONTROL__WARM_RST__MASK 0x00000004U #define RESET_CONTROL__WARM_RST__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define RESET_CONTROL__WARM_RST__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define RESET_CONTROL__WARM_RST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define RESET_CONTROL__WARM_RST__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define RESET_CONTROL__WARM_RST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field COLD_RST */ #define RESET_CONTROL__COLD_RST__SHIFT 3 #define RESET_CONTROL__COLD_RST__WIDTH 1 #define RESET_CONTROL__COLD_RST__MASK 0x00000008U #define RESET_CONTROL__COLD_RST__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define RESET_CONTROL__COLD_RST__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define RESET_CONTROL__COLD_RST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define RESET_CONTROL__COLD_RST__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define RESET_CONTROL__COLD_RST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) #define RESET_CONTROL__TYPE u_int32_t #define RESET_CONTROL__READ 0x0000000fU #define RESET_CONTROL__WRITE 0x0000000fU #endif /* __RESET_CONTROL_MACRO__ */ /* macros for rtc_reg_map.RESET_CONTROL */ #define INST_RTC_REG_MAP__RESET_CONTROL__NUM 1 /* macros for BlueprintGlobalNameSpace::XTAL_CONTROL */ #ifndef __XTAL_CONTROL_MACRO__ #define __XTAL_CONTROL_MACRO__ /* macros for field TCXO */ #define XTAL_CONTROL__TCXO__SHIFT 0 #define XTAL_CONTROL__TCXO__WIDTH 1 #define XTAL_CONTROL__TCXO__MASK 0x00000001U #define XTAL_CONTROL__TCXO__READ(src) (u_int32_t)(src) & 0x00000001U #define XTAL_CONTROL__TCXO__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define XTAL_CONTROL__TCXO__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define XTAL_CONTROL__TCXO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) #define XTAL_CONTROL__TCXO__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define XTAL_CONTROL__TCXO__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) #define XTAL_CONTROL__TYPE u_int32_t #define XTAL_CONTROL__READ 0x00000001U #define XTAL_CONTROL__WRITE 0x00000001U #endif /* __XTAL_CONTROL_MACRO__ */ /* macros for rtc_reg_map.XTAL_CONTROL */ #define INST_RTC_REG_MAP__XTAL_CONTROL__NUM 1 /* macros for BlueprintGlobalNameSpace::REG_CONTROL0 */ #ifndef __REG_CONTROL0_MACRO__ #define __REG_CONTROL0_MACRO__ /* macros for field SWREG_BITS */ #define REG_CONTROL0__SWREG_BITS__SHIFT 0 #define REG_CONTROL0__SWREG_BITS__WIDTH 32 #define REG_CONTROL0__SWREG_BITS__MASK 0xffffffffU #define REG_CONTROL0__SWREG_BITS__READ(src) (u_int32_t)(src) & 0xffffffffU #define REG_CONTROL0__SWREG_BITS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define REG_CONTROL0__SWREG_BITS__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define REG_CONTROL0__TYPE u_int32_t #define REG_CONTROL0__READ 0xffffffffU #define REG_CONTROL0__WRITE 0xffffffffU #endif /* __REG_CONTROL0_MACRO__ */ /* macros for rtc_reg_map.REG_CONTROL0 */ #define INST_RTC_REG_MAP__REG_CONTROL0__NUM 1 /* macros for BlueprintGlobalNameSpace::REG_CONTROL1 */ #ifndef __REG_CONTROL1_MACRO__ #define __REG_CONTROL1_MACRO__ /* macros for field SWREG_PROGRAM */ #define REG_CONTROL1__SWREG_PROGRAM__SHIFT 0 #define REG_CONTROL1__SWREG_PROGRAM__WIDTH 1 #define REG_CONTROL1__SWREG_PROGRAM__MASK 0x00000001U #define REG_CONTROL1__SWREG_PROGRAM__READ(src) (u_int32_t)(src) & 0x00000001U #define REG_CONTROL1__SWREG_PROGRAM__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define REG_CONTROL1__SWREG_PROGRAM__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define REG_CONTROL1__SWREG_PROGRAM__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define REG_CONTROL1__SWREG_PROGRAM__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field OTPREG_LVL */ #define REG_CONTROL1__OTPREG_LVL__SHIFT 1 #define REG_CONTROL1__OTPREG_LVL__WIDTH 2 #define REG_CONTROL1__OTPREG_LVL__MASK 0x00000006U #define REG_CONTROL1__OTPREG_LVL__READ(src) \ (((u_int32_t)(src)\ & 0x00000006U) >> 1) #define REG_CONTROL1__OTPREG_LVL__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000006U) #define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000006U) | (((u_int32_t)(src) <<\ 1) & 0x00000006U) #define REG_CONTROL1__OTPREG_LVL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000006U))) #define REG_CONTROL1__TYPE u_int32_t #define REG_CONTROL1__READ 0x00000007U #define REG_CONTROL1__WRITE 0x00000007U #endif /* __REG_CONTROL1_MACRO__ */ /* macros for rtc_reg_map.REG_CONTROL1 */ #define INST_RTC_REG_MAP__REG_CONTROL1__NUM 1 /* macros for BlueprintGlobalNameSpace::QUADRATURE */ #ifndef __QUADRATURE_MACRO__ #define __QUADRATURE_MACRO__ /* macros for field DAC */ #define QUADRATURE__DAC__SHIFT 0 #define QUADRATURE__DAC__WIDTH 3 #define QUADRATURE__DAC__MASK 0x00000007U #define QUADRATURE__DAC__READ(src) (u_int32_t)(src) & 0x00000007U #define QUADRATURE__DAC__WRITE(src) ((u_int32_t)(src) & 0x00000007U) #define QUADRATURE__DAC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000007U) | ((u_int32_t)(src) &\ 0x00000007U) #define QUADRATURE__DAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) /* macros for field ADC */ #define QUADRATURE__ADC__SHIFT 4 #define QUADRATURE__ADC__WIDTH 4 #define QUADRATURE__ADC__MASK 0x000000f0U #define QUADRATURE__ADC__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) #define QUADRATURE__ADC__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) #define QUADRATURE__ADC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000f0U) | (((u_int32_t)(src) <<\ 4) & 0x000000f0U) #define QUADRATURE__ADC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x000000f0U))) #define QUADRATURE__TYPE u_int32_t #define QUADRATURE__READ 0x000000f7U #define QUADRATURE__WRITE 0x000000f7U #endif /* __QUADRATURE_MACRO__ */ /* macros for rtc_reg_map.QUADRATURE */ #define INST_RTC_REG_MAP__QUADRATURE__NUM 1 /* macros for BlueprintGlobalNameSpace::PLL_CONTROL */ #ifndef __PLL_CONTROL_MACRO__ #define __PLL_CONTROL_MACRO__ /* macros for field DIV_INT */ #define PLL_CONTROL__DIV_INT__SHIFT 0 #define PLL_CONTROL__DIV_INT__WIDTH 6 #define PLL_CONTROL__DIV_INT__MASK 0x0000003fU #define PLL_CONTROL__DIV_INT__READ(src) (u_int32_t)(src) & 0x0000003fU #define PLL_CONTROL__DIV_INT__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) #define PLL_CONTROL__DIV_INT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000003fU) | ((u_int32_t)(src) &\ 0x0000003fU) #define PLL_CONTROL__DIV_INT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000003fU))) /* macros for field DIV_FRAC */ #define PLL_CONTROL__DIV_FRAC__SHIFT 6 #define PLL_CONTROL__DIV_FRAC__WIDTH 14 #define PLL_CONTROL__DIV_FRAC__MASK 0x000fffc0U #define PLL_CONTROL__DIV_FRAC__READ(src) \ (((u_int32_t)(src)\ & 0x000fffc0U) >> 6) #define PLL_CONTROL__DIV_FRAC__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x000fffc0U) #define PLL_CONTROL__DIV_FRAC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000fffc0U) | (((u_int32_t)(src) <<\ 6) & 0x000fffc0U) #define PLL_CONTROL__DIV_FRAC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x000fffc0U))) /* macros for field REFDIV */ #define PLL_CONTROL__REFDIV__SHIFT 20 #define PLL_CONTROL__REFDIV__WIDTH 5 #define PLL_CONTROL__REFDIV__MASK 0x01f00000U #define PLL_CONTROL__REFDIV__READ(src) (((u_int32_t)(src) & 0x01f00000U) >> 20) #define PLL_CONTROL__REFDIV__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x01f00000U) #define PLL_CONTROL__REFDIV__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01f00000U) | (((u_int32_t)(src) <<\ 20) & 0x01f00000U) #define PLL_CONTROL__REFDIV__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x01f00000U))) /* macros for field CLK_SEL */ #define PLL_CONTROL__CLK_SEL__SHIFT 25 #define PLL_CONTROL__CLK_SEL__WIDTH 2 #define PLL_CONTROL__CLK_SEL__MASK 0x06000000U #define PLL_CONTROL__CLK_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x06000000U) >> 25) #define PLL_CONTROL__CLK_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x06000000U) #define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x06000000U) | (((u_int32_t)(src) <<\ 25) & 0x06000000U) #define PLL_CONTROL__CLK_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x06000000U))) /* macros for field BYPASS */ #define PLL_CONTROL__BYPASS__SHIFT 27 #define PLL_CONTROL__BYPASS__WIDTH 1 #define PLL_CONTROL__BYPASS__MASK 0x08000000U #define PLL_CONTROL__BYPASS__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) #define PLL_CONTROL__BYPASS__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define PLL_CONTROL__BYPASS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define PLL_CONTROL__BYPASS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define PLL_CONTROL__BYPASS__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define PLL_CONTROL__BYPASS__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field UPDATING */ #define PLL_CONTROL__UPDATING__SHIFT 28 #define PLL_CONTROL__UPDATING__WIDTH 1 #define PLL_CONTROL__UPDATING__MASK 0x10000000U #define PLL_CONTROL__UPDATING__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define PLL_CONTROL__UPDATING__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define PLL_CONTROL__UPDATING__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field NOPWD */ #define PLL_CONTROL__NOPWD__SHIFT 29 #define PLL_CONTROL__NOPWD__WIDTH 1 #define PLL_CONTROL__NOPWD__MASK 0x20000000U #define PLL_CONTROL__NOPWD__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) #define PLL_CONTROL__NOPWD__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) #define PLL_CONTROL__NOPWD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define PLL_CONTROL__NOPWD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define PLL_CONTROL__NOPWD__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define PLL_CONTROL__NOPWD__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field MAC_OVERRIDE */ #define PLL_CONTROL__MAC_OVERRIDE__SHIFT 30 #define PLL_CONTROL__MAC_OVERRIDE__WIDTH 1 #define PLL_CONTROL__MAC_OVERRIDE__MASK 0x40000000U #define PLL_CONTROL__MAC_OVERRIDE__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define PLL_CONTROL__MAC_OVERRIDE__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define PLL_CONTROL__MAC_OVERRIDE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define PLL_CONTROL__MAC_OVERRIDE__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define PLL_CONTROL__MAC_OVERRIDE__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) #define PLL_CONTROL__TYPE u_int32_t #define PLL_CONTROL__READ 0x7fffffffU #define PLL_CONTROL__WRITE 0x7fffffffU #endif /* __PLL_CONTROL_MACRO__ */ /* macros for rtc_reg_map.PLL_CONTROL */ #define INST_RTC_REG_MAP__PLL_CONTROL__NUM 1 /* macros for BlueprintGlobalNameSpace::PLL_SETTLE */ #ifndef __PLL_SETTLE_MACRO__ #define __PLL_SETTLE_MACRO__ /* macros for field TIME */ #define PLL_SETTLE__TIME__SHIFT 0 #define PLL_SETTLE__TIME__WIDTH 11 #define PLL_SETTLE__TIME__MASK 0x000007ffU #define PLL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x000007ffU #define PLL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x000007ffU) #define PLL_SETTLE__TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000007ffU) | ((u_int32_t)(src) &\ 0x000007ffU) #define PLL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x000007ffU))) #define PLL_SETTLE__TYPE u_int32_t #define PLL_SETTLE__READ 0x000007ffU #define PLL_SETTLE__WRITE 0x000007ffU #endif /* __PLL_SETTLE_MACRO__ */ /* macros for rtc_reg_map.PLL_SETTLE */ #define INST_RTC_REG_MAP__PLL_SETTLE__NUM 1 /* macros for BlueprintGlobalNameSpace::XTAL_SETTLE */ #ifndef __XTAL_SETTLE_MACRO__ #define __XTAL_SETTLE_MACRO__ /* macros for field TIME */ #define XTAL_SETTLE__TIME__SHIFT 0 #define XTAL_SETTLE__TIME__WIDTH 7 #define XTAL_SETTLE__TIME__MASK 0x0000007fU #define XTAL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x0000007fU #define XTAL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) #define XTAL_SETTLE__TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000007fU) | ((u_int32_t)(src) &\ 0x0000007fU) #define XTAL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) #define XTAL_SETTLE__TYPE u_int32_t #define XTAL_SETTLE__READ 0x0000007fU #define XTAL_SETTLE__WRITE 0x0000007fU #endif /* __XTAL_SETTLE_MACRO__ */ /* macros for rtc_reg_map.XTAL_SETTLE */ #define INST_RTC_REG_MAP__XTAL_SETTLE__NUM 1 /* macros for BlueprintGlobalNameSpace::CLOCK_OUT */ #ifndef __CLOCK_OUT_MACRO__ #define __CLOCK_OUT_MACRO__ /* macros for field SELECT */ #define CLOCK_OUT__SELECT__SHIFT 0 #define CLOCK_OUT__SELECT__WIDTH 4 #define CLOCK_OUT__SELECT__MASK 0x0000000fU #define CLOCK_OUT__SELECT__READ(src) (u_int32_t)(src) & 0x0000000fU #define CLOCK_OUT__SELECT__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) #define CLOCK_OUT__SELECT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define CLOCK_OUT__SELECT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) /* macros for field DELAY */ #define CLOCK_OUT__DELAY__SHIFT 4 #define CLOCK_OUT__DELAY__WIDTH 3 #define CLOCK_OUT__DELAY__MASK 0x00000070U #define CLOCK_OUT__DELAY__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) #define CLOCK_OUT__DELAY__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000070U) #define CLOCK_OUT__DELAY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000070U) | (((u_int32_t)(src) <<\ 4) & 0x00000070U) #define CLOCK_OUT__DELAY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000070U))) #define CLOCK_OUT__TYPE u_int32_t #define CLOCK_OUT__READ 0x0000007fU #define CLOCK_OUT__WRITE 0x0000007fU #endif /* __CLOCK_OUT_MACRO__ */ /* macros for rtc_reg_map.CLOCK_OUT */ #define INST_RTC_REG_MAP__CLOCK_OUT__NUM 1 /* macros for BlueprintGlobalNameSpace::BIAS_OVERRIDE */ #ifndef __BIAS_OVERRIDE_MACRO__ #define __BIAS_OVERRIDE_MACRO__ /* macros for field ON */ #define BIAS_OVERRIDE__ON__SHIFT 0 #define BIAS_OVERRIDE__ON__WIDTH 1 #define BIAS_OVERRIDE__ON__MASK 0x00000001U #define BIAS_OVERRIDE__ON__READ(src) (u_int32_t)(src) & 0x00000001U #define BIAS_OVERRIDE__ON__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define BIAS_OVERRIDE__ON__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define BIAS_OVERRIDE__ON__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) #define BIAS_OVERRIDE__ON__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define BIAS_OVERRIDE__ON__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) #define BIAS_OVERRIDE__TYPE u_int32_t #define BIAS_OVERRIDE__READ 0x00000001U #define BIAS_OVERRIDE__WRITE 0x00000001U #endif /* __BIAS_OVERRIDE_MACRO__ */ /* macros for rtc_reg_map.BIAS_OVERRIDE */ #define INST_RTC_REG_MAP__BIAS_OVERRIDE__NUM 1 /* macros for BlueprintGlobalNameSpace::RESET_CAUSE */ #ifndef __RESET_CAUSE_MACRO__ #define __RESET_CAUSE_MACRO__ /* macros for field LAST */ #define RESET_CAUSE__LAST__SHIFT 0 #define RESET_CAUSE__LAST__WIDTH 2 #define RESET_CAUSE__LAST__MASK 0x00000003U #define RESET_CAUSE__LAST__READ(src) (u_int32_t)(src) & 0x00000003U #define RESET_CAUSE__TYPE u_int32_t #define RESET_CAUSE__READ 0x00000003U #endif /* __RESET_CAUSE_MACRO__ */ /* macros for rtc_reg_map.RESET_CAUSE */ #define INST_RTC_REG_MAP__RESET_CAUSE__NUM 1 /* macros for BlueprintGlobalNameSpace::SYSTEM_SLEEP */ #ifndef __SYSTEM_SLEEP_MACRO__ #define __SYSTEM_SLEEP_MACRO__ /* macros for field DISABLE */ #define SYSTEM_SLEEP__DISABLE__SHIFT 0 #define SYSTEM_SLEEP__DISABLE__WIDTH 1 #define SYSTEM_SLEEP__DISABLE__MASK 0x00000001U #define SYSTEM_SLEEP__DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U #define SYSTEM_SLEEP__DISABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define SYSTEM_SLEEP__DISABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define SYSTEM_SLEEP__DISABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define SYSTEM_SLEEP__DISABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field LIGHT */ #define SYSTEM_SLEEP__LIGHT__SHIFT 1 #define SYSTEM_SLEEP__LIGHT__WIDTH 1 #define SYSTEM_SLEEP__LIGHT__MASK 0x00000002U #define SYSTEM_SLEEP__LIGHT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) #define SYSTEM_SLEEP__LIGHT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) #define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define SYSTEM_SLEEP__LIGHT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define SYSTEM_SLEEP__LIGHT__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define SYSTEM_SLEEP__LIGHT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field MAC_IF */ #define SYSTEM_SLEEP__MAC_IF__SHIFT 2 #define SYSTEM_SLEEP__MAC_IF__WIDTH 1 #define SYSTEM_SLEEP__MAC_IF__MASK 0x00000004U #define SYSTEM_SLEEP__MAC_IF__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) #define SYSTEM_SLEEP__MAC_IF__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define SYSTEM_SLEEP__MAC_IF__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) #define SYSTEM_SLEEP__TYPE u_int32_t #define SYSTEM_SLEEP__READ 0x00000007U #define SYSTEM_SLEEP__WRITE 0x00000007U #endif /* __SYSTEM_SLEEP_MACRO__ */ /* macros for rtc_reg_map.SYSTEM_SLEEP */ #define INST_RTC_REG_MAP__SYSTEM_SLEEP__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_SLEEP_CONTROL */ #ifndef __MAC_SLEEP_CONTROL_MACRO__ #define __MAC_SLEEP_CONTROL_MACRO__ /* macros for field ENABLE */ #define MAC_SLEEP_CONTROL__ENABLE__SHIFT 0 #define MAC_SLEEP_CONTROL__ENABLE__WIDTH 2 #define MAC_SLEEP_CONTROL__ENABLE__MASK 0x00000003U #define MAC_SLEEP_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000003U #define MAC_SLEEP_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) #define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000003U) | ((u_int32_t)(src) &\ 0x00000003U) #define MAC_SLEEP_CONTROL__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000003U))) #define MAC_SLEEP_CONTROL__TYPE u_int32_t #define MAC_SLEEP_CONTROL__READ 0x00000003U #define MAC_SLEEP_CONTROL__WRITE 0x00000003U #endif /* __MAC_SLEEP_CONTROL_MACRO__ */ /* macros for rtc_reg_map.MAC_SLEEP_CONTROL */ #define INST_RTC_REG_MAP__MAC_SLEEP_CONTROL__NUM 1 /* macros for BlueprintGlobalNameSpace::KEEP_AWAKE */ #ifndef __KEEP_AWAKE_MACRO__ #define __KEEP_AWAKE_MACRO__ /* macros for field COUNT */ #define KEEP_AWAKE__COUNT__SHIFT 0 #define KEEP_AWAKE__COUNT__WIDTH 8 #define KEEP_AWAKE__COUNT__MASK 0x000000ffU #define KEEP_AWAKE__COUNT__READ(src) (u_int32_t)(src) & 0x000000ffU #define KEEP_AWAKE__COUNT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define KEEP_AWAKE__COUNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define KEEP_AWAKE__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) #define KEEP_AWAKE__TYPE u_int32_t #define KEEP_AWAKE__READ 0x000000ffU #define KEEP_AWAKE__WRITE 0x000000ffU #endif /* __KEEP_AWAKE_MACRO__ */ /* macros for rtc_reg_map.KEEP_AWAKE */ #define INST_RTC_REG_MAP__KEEP_AWAKE__NUM 1 /* macros for BlueprintGlobalNameSpace::DERIVED_RTC_CLK */ #ifndef __DERIVED_RTC_CLK_MACRO__ #define __DERIVED_RTC_CLK_MACRO__ /* macros for field PERIOD */ #define DERIVED_RTC_CLK__PERIOD__SHIFT 1 #define DERIVED_RTC_CLK__PERIOD__WIDTH 15 #define DERIVED_RTC_CLK__PERIOD__MASK 0x0000fffeU #define DERIVED_RTC_CLK__PERIOD__READ(src) \ (((u_int32_t)(src)\ & 0x0000fffeU) >> 1) #define DERIVED_RTC_CLK__PERIOD__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x0000fffeU) #define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000fffeU) | (((u_int32_t)(src) <<\ 1) & 0x0000fffeU) #define DERIVED_RTC_CLK__PERIOD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x0000fffeU))) /* macros for field EXTERNAL_DETECT */ #define DERIVED_RTC_CLK__EXTERNAL_DETECT__SHIFT 18 #define DERIVED_RTC_CLK__EXTERNAL_DETECT__WIDTH 1 #define DERIVED_RTC_CLK__EXTERNAL_DETECT__MASK 0x00040000U #define DERIVED_RTC_CLK__EXTERNAL_DETECT__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define DERIVED_RTC_CLK__EXTERNAL_DETECT__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define DERIVED_RTC_CLK__EXTERNAL_DETECT__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) #define DERIVED_RTC_CLK__TYPE u_int32_t #define DERIVED_RTC_CLK__READ 0x0004fffeU #define DERIVED_RTC_CLK__WRITE 0x0004fffeU #endif /* __DERIVED_RTC_CLK_MACRO__ */ /* macros for rtc_reg_map.DERIVED_RTC_CLK */ #define INST_RTC_REG_MAP__DERIVED_RTC_CLK__NUM 1 /* macros for BlueprintGlobalNameSpace::PLL_CONTROL2 */ #ifndef __PLL_CONTROL2_MACRO__ #define __PLL_CONTROL2_MACRO__ /* macros for field DIV_INT */ #define PLL_CONTROL2__DIV_INT__SHIFT 0 #define PLL_CONTROL2__DIV_INT__WIDTH 3 #define PLL_CONTROL2__DIV_INT__MASK 0x00000007U #define PLL_CONTROL2__DIV_INT__READ(src) (u_int32_t)(src) & 0x00000007U #define PLL_CONTROL2__DIV_INT__WRITE(src) ((u_int32_t)(src) & 0x00000007U) #define PLL_CONTROL2__DIV_INT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000007U) | ((u_int32_t)(src) &\ 0x00000007U) #define PLL_CONTROL2__DIV_INT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000007U))) /* macros for field DIV_FRAC */ #define PLL_CONTROL2__DIV_FRAC__SHIFT 3 #define PLL_CONTROL2__DIV_FRAC__WIDTH 4 #define PLL_CONTROL2__DIV_FRAC__MASK 0x00000078U #define PLL_CONTROL2__DIV_FRAC__READ(src) \ (((u_int32_t)(src)\ & 0x00000078U) >> 3) #define PLL_CONTROL2__DIV_FRAC__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000078U) #define PLL_CONTROL2__DIV_FRAC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000078U) | (((u_int32_t)(src) <<\ 3) & 0x00000078U) #define PLL_CONTROL2__DIV_FRAC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000078U))) #define PLL_CONTROL2__TYPE u_int32_t #define PLL_CONTROL2__READ 0x0000007fU #define PLL_CONTROL2__WRITE 0x0000007fU #endif /* __PLL_CONTROL2_MACRO__ */ /* macros for rtc_reg_map.PLL_CONTROL2 */ #define INST_RTC_REG_MAP__PLL_CONTROL2__NUM 1 /* macros for BlueprintGlobalNameSpace::RTC_SYNC_RESET */ #ifndef __RTC_SYNC_RESET_MACRO__ #define __RTC_SYNC_RESET_MACRO__ /* macros for field RESET_L */ #define RTC_SYNC_RESET__RESET_L__SHIFT 0 #define RTC_SYNC_RESET__RESET_L__WIDTH 1 #define RTC_SYNC_RESET__RESET_L__MASK 0x00000001U #define RTC_SYNC_RESET__RESET_L__READ(src) (u_int32_t)(src) & 0x00000001U #define RTC_SYNC_RESET__RESET_L__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define RTC_SYNC_RESET__RESET_L__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define RTC_SYNC_RESET__RESET_L__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RTC_SYNC_RESET__RESET_L__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) #define RTC_SYNC_RESET__TYPE u_int32_t #define RTC_SYNC_RESET__READ 0x00000001U #define RTC_SYNC_RESET__WRITE 0x00000001U #endif /* __RTC_SYNC_RESET_MACRO__ */ /* macros for rtc_sync_reg_map.RTC_SYNC_RESET */ #define INST_RTC_SYNC_REG_MAP__RTC_SYNC_RESET__NUM 1 /* macros for BlueprintGlobalNameSpace::RTC_SYNC_STATUS */ #ifndef __RTC_SYNC_STATUS_MACRO__ #define __RTC_SYNC_STATUS_MACRO__ /* macros for field SHUTDOWN_STATE */ #define RTC_SYNC_STATUS__SHUTDOWN_STATE__SHIFT 0 #define RTC_SYNC_STATUS__SHUTDOWN_STATE__WIDTH 1 #define RTC_SYNC_STATUS__SHUTDOWN_STATE__MASK 0x00000001U #define RTC_SYNC_STATUS__SHUTDOWN_STATE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define RTC_SYNC_STATUS__SHUTDOWN_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RTC_SYNC_STATUS__SHUTDOWN_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field ON_STATE */ #define RTC_SYNC_STATUS__ON_STATE__SHIFT 1 #define RTC_SYNC_STATUS__ON_STATE__WIDTH 1 #define RTC_SYNC_STATUS__ON_STATE__MASK 0x00000002U #define RTC_SYNC_STATUS__ON_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define RTC_SYNC_STATUS__ON_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define RTC_SYNC_STATUS__ON_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field SLEEP_STATE */ #define RTC_SYNC_STATUS__SLEEP_STATE__SHIFT 2 #define RTC_SYNC_STATUS__SLEEP_STATE__WIDTH 1 #define RTC_SYNC_STATUS__SLEEP_STATE__MASK 0x00000004U #define RTC_SYNC_STATUS__SLEEP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define RTC_SYNC_STATUS__SLEEP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define RTC_SYNC_STATUS__SLEEP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field WAKEUP_STATE */ #define RTC_SYNC_STATUS__WAKEUP_STATE__SHIFT 3 #define RTC_SYNC_STATUS__WAKEUP_STATE__WIDTH 1 #define RTC_SYNC_STATUS__WAKEUP_STATE__MASK 0x00000008U #define RTC_SYNC_STATUS__WAKEUP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define RTC_SYNC_STATUS__WAKEUP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define RTC_SYNC_STATUS__WAKEUP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field WRESET */ #define RTC_SYNC_STATUS__WRESET__SHIFT 4 #define RTC_SYNC_STATUS__WRESET__WIDTH 1 #define RTC_SYNC_STATUS__WRESET__MASK 0x00000010U #define RTC_SYNC_STATUS__WRESET__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define RTC_SYNC_STATUS__WRESET__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define RTC_SYNC_STATUS__WRESET__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field PLL_CHANGING */ #define RTC_SYNC_STATUS__PLL_CHANGING__SHIFT 5 #define RTC_SYNC_STATUS__PLL_CHANGING__WIDTH 1 #define RTC_SYNC_STATUS__PLL_CHANGING__MASK 0x00000020U #define RTC_SYNC_STATUS__PLL_CHANGING__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define RTC_SYNC_STATUS__PLL_CHANGING__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define RTC_SYNC_STATUS__PLL_CHANGING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) #define RTC_SYNC_STATUS__TYPE u_int32_t #define RTC_SYNC_STATUS__READ 0x0000003fU #endif /* __RTC_SYNC_STATUS_MACRO__ */ /* macros for rtc_sync_reg_map.RTC_SYNC_STATUS */ #define INST_RTC_SYNC_REG_MAP__RTC_SYNC_STATUS__NUM 1 /* macros for BlueprintGlobalNameSpace::RTC_SYNC_DERIVED */ #ifndef __RTC_SYNC_DERIVED_MACRO__ #define __RTC_SYNC_DERIVED_MACRO__ /* macros for field BYPASS */ #define RTC_SYNC_DERIVED__BYPASS__SHIFT 0 #define RTC_SYNC_DERIVED__BYPASS__WIDTH 1 #define RTC_SYNC_DERIVED__BYPASS__MASK 0x00000001U #define RTC_SYNC_DERIVED__BYPASS__READ(src) (u_int32_t)(src) & 0x00000001U #define RTC_SYNC_DERIVED__BYPASS__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define RTC_SYNC_DERIVED__BYPASS__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define RTC_SYNC_DERIVED__BYPASS__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RTC_SYNC_DERIVED__BYPASS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field FORCE */ #define RTC_SYNC_DERIVED__FORCE__SHIFT 1 #define RTC_SYNC_DERIVED__FORCE__WIDTH 1 #define RTC_SYNC_DERIVED__FORCE__MASK 0x00000002U #define RTC_SYNC_DERIVED__FORCE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define RTC_SYNC_DERIVED__FORCE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define RTC_SYNC_DERIVED__FORCE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define RTC_SYNC_DERIVED__FORCE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define RTC_SYNC_DERIVED__FORCE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) #define RTC_SYNC_DERIVED__TYPE u_int32_t #define RTC_SYNC_DERIVED__READ 0x00000003U #define RTC_SYNC_DERIVED__WRITE 0x00000003U #endif /* __RTC_SYNC_DERIVED_MACRO__ */ /* macros for rtc_sync_reg_map.RTC_SYNC_DERIVED */ #define INST_RTC_SYNC_REG_MAP__RTC_SYNC_DERIVED__NUM 1 /* macros for BlueprintGlobalNameSpace::RTC_SYNC_FORCE_WAKE */ #ifndef __RTC_SYNC_FORCE_WAKE_MACRO__ #define __RTC_SYNC_FORCE_WAKE_MACRO__ /* macros for field ENABLE */ #define RTC_SYNC_FORCE_WAKE__ENABLE__SHIFT 0 #define RTC_SYNC_FORCE_WAKE__ENABLE__WIDTH 1 #define RTC_SYNC_FORCE_WAKE__ENABLE__MASK 0x00000001U #define RTC_SYNC_FORCE_WAKE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U #define RTC_SYNC_FORCE_WAKE__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RTC_SYNC_FORCE_WAKE__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field INTR */ #define RTC_SYNC_FORCE_WAKE__INTR__SHIFT 1 #define RTC_SYNC_FORCE_WAKE__INTR__WIDTH 1 #define RTC_SYNC_FORCE_WAKE__INTR__MASK 0x00000002U #define RTC_SYNC_FORCE_WAKE__INTR__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define RTC_SYNC_FORCE_WAKE__INTR__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define RTC_SYNC_FORCE_WAKE__INTR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define RTC_SYNC_FORCE_WAKE__INTR__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define RTC_SYNC_FORCE_WAKE__INTR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) #define RTC_SYNC_FORCE_WAKE__TYPE u_int32_t #define RTC_SYNC_FORCE_WAKE__READ 0x00000003U #define RTC_SYNC_FORCE_WAKE__WRITE 0x00000003U #endif /* __RTC_SYNC_FORCE_WAKE_MACRO__ */ /* macros for rtc_sync_reg_map.RTC_SYNC_FORCE_WAKE */ #define INST_RTC_SYNC_REG_MAP__RTC_SYNC_FORCE_WAKE__NUM 1 /* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_CAUSE */ #ifndef __RTC_SYNC_INTR_CAUSE_MACRO__ #define __RTC_SYNC_INTR_CAUSE_MACRO__ /* macros for field SHUTDOWN_STATE */ #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SHIFT 0 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WIDTH 1 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MASK 0x00000001U #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field ON_STATE */ #define RTC_SYNC_INTR_CAUSE__ON_STATE__SHIFT 1 #define RTC_SYNC_INTR_CAUSE__ON_STATE__WIDTH 1 #define RTC_SYNC_INTR_CAUSE__ON_STATE__MASK 0x00000002U #define RTC_SYNC_INTR_CAUSE__ON_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define RTC_SYNC_INTR_CAUSE__ON_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define RTC_SYNC_INTR_CAUSE__ON_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define RTC_SYNC_INTR_CAUSE__ON_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define RTC_SYNC_INTR_CAUSE__ON_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field SLEEP_STATE */ #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SHIFT 2 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WIDTH 1 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MASK 0x00000004U #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field WAKEUP_STATE */ #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SHIFT 3 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WIDTH 1 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MASK 0x00000008U #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field SLEEP_ACCESS */ #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SHIFT 4 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WIDTH 1 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MASK 0x00000010U #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field PLL_CHANGING */ #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SHIFT 5 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WIDTH 1 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MASK 0x00000020U #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) #define RTC_SYNC_INTR_CAUSE__TYPE u_int32_t #define RTC_SYNC_INTR_CAUSE__READ 0x0000003fU #define RTC_SYNC_INTR_CAUSE__WRITE 0x0000003fU #endif /* __RTC_SYNC_INTR_CAUSE_MACRO__ */ /* macros for rtc_sync_reg_map.RTC_SYNC_INTR_CAUSE */ #define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_CAUSE__NUM 1 /* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_ENABLE */ #ifndef __RTC_SYNC_INTR_ENABLE_MACRO__ #define __RTC_SYNC_INTR_ENABLE_MACRO__ /* macros for field SHUTDOWN_STATE */ #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SHIFT 0 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WIDTH 1 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MASK 0x00000001U #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field ON_STATE */ #define RTC_SYNC_INTR_ENABLE__ON_STATE__SHIFT 1 #define RTC_SYNC_INTR_ENABLE__ON_STATE__WIDTH 1 #define RTC_SYNC_INTR_ENABLE__ON_STATE__MASK 0x00000002U #define RTC_SYNC_INTR_ENABLE__ON_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define RTC_SYNC_INTR_ENABLE__ON_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define RTC_SYNC_INTR_ENABLE__ON_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define RTC_SYNC_INTR_ENABLE__ON_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define RTC_SYNC_INTR_ENABLE__ON_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field SLEEP_STATE */ #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SHIFT 2 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WIDTH 1 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MASK 0x00000004U #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field WAKEUP_STATE */ #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SHIFT 3 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WIDTH 1 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MASK 0x00000008U #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field SLEEP_ACCESS */ #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SHIFT 4 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WIDTH 1 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MASK 0x00000010U #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field PLL_CHANGING */ #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SHIFT 5 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WIDTH 1 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MASK 0x00000020U #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) #define RTC_SYNC_INTR_ENABLE__TYPE u_int32_t #define RTC_SYNC_INTR_ENABLE__READ 0x0000003fU #define RTC_SYNC_INTR_ENABLE__WRITE 0x0000003fU #endif /* __RTC_SYNC_INTR_ENABLE_MACRO__ */ /* macros for rtc_sync_reg_map.RTC_SYNC_INTR_ENABLE */ #define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_ENABLE__NUM 1 /* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_MASK */ #ifndef __RTC_SYNC_INTR_MASK_MACRO__ #define __RTC_SYNC_INTR_MASK_MACRO__ /* macros for field SHUTDOWN_STATE */ #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SHIFT 0 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WIDTH 1 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MASK 0x00000001U #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field ON_STATE */ #define RTC_SYNC_INTR_MASK__ON_STATE__SHIFT 1 #define RTC_SYNC_INTR_MASK__ON_STATE__WIDTH 1 #define RTC_SYNC_INTR_MASK__ON_STATE__MASK 0x00000002U #define RTC_SYNC_INTR_MASK__ON_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define RTC_SYNC_INTR_MASK__ON_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define RTC_SYNC_INTR_MASK__ON_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define RTC_SYNC_INTR_MASK__ON_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define RTC_SYNC_INTR_MASK__ON_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field SLEEP_STATE */ #define RTC_SYNC_INTR_MASK__SLEEP_STATE__SHIFT 2 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__WIDTH 1 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__MASK 0x00000004U #define RTC_SYNC_INTR_MASK__SLEEP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define RTC_SYNC_INTR_MASK__SLEEP_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define RTC_SYNC_INTR_MASK__SLEEP_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define RTC_SYNC_INTR_MASK__SLEEP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define RTC_SYNC_INTR_MASK__SLEEP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field WAKEUP_STATE */ #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SHIFT 3 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WIDTH 1 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MASK 0x00000008U #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field SLEEP_ACCESS */ #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SHIFT 4 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WIDTH 1 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MASK 0x00000010U #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field PLL_CHANGING */ #define RTC_SYNC_INTR_MASK__PLL_CHANGING__SHIFT 5 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__WIDTH 1 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__MASK 0x00000020U #define RTC_SYNC_INTR_MASK__PLL_CHANGING__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define RTC_SYNC_INTR_MASK__PLL_CHANGING__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define RTC_SYNC_INTR_MASK__PLL_CHANGING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define RTC_SYNC_INTR_MASK__PLL_CHANGING__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define RTC_SYNC_INTR_MASK__PLL_CHANGING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) #define RTC_SYNC_INTR_MASK__TYPE u_int32_t #define RTC_SYNC_INTR_MASK__READ 0x0000003fU #define RTC_SYNC_INTR_MASK__WRITE 0x0000003fU #endif /* __RTC_SYNC_INTR_MASK_MACRO__ */ /* macros for rtc_sync_reg_map.RTC_SYNC_INTR_MASK */ #define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_L32 */ #ifndef __MAC_PCU_STA_ADDR_L32_MACRO__ #define __MAC_PCU_STA_ADDR_L32_MACRO__ /* macros for field ADDR_31_0 */ #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__SHIFT 0 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WIDTH 32 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MASK 0xffffffffU #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_STA_ADDR_L32__TYPE u_int32_t #define MAC_PCU_STA_ADDR_L32__READ 0xffffffffU #define MAC_PCU_STA_ADDR_L32__WRITE 0xffffffffU #endif /* __MAC_PCU_STA_ADDR_L32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_L32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_L32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_U16 */ #ifndef __MAC_PCU_STA_ADDR_U16_MACRO__ #define __MAC_PCU_STA_ADDR_U16_MACRO__ /* macros for field ADDR_47_32 */ #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__SHIFT 0 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WIDTH 16 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MASK 0x0000ffffU #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field STA_AP */ #define MAC_PCU_STA_ADDR_U16__STA_AP__SHIFT 16 #define MAC_PCU_STA_ADDR_U16__STA_AP__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__STA_AP__MASK 0x00010000U #define MAC_PCU_STA_ADDR_U16__STA_AP__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_STA_ADDR_U16__STA_AP__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_STA_ADDR_U16__STA_AP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_STA_ADDR_U16__STA_AP__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_STA_ADDR_U16__STA_AP__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field ADHOC */ #define MAC_PCU_STA_ADDR_U16__ADHOC__SHIFT 17 #define MAC_PCU_STA_ADDR_U16__ADHOC__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__ADHOC__MASK 0x00020000U #define MAC_PCU_STA_ADDR_U16__ADHOC__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_STA_ADDR_U16__ADHOC__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_STA_ADDR_U16__ADHOC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_STA_ADDR_U16__ADHOC__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_STA_ADDR_U16__ADHOC__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field PW_SAVE */ #define MAC_PCU_STA_ADDR_U16__PW_SAVE__SHIFT 18 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__MASK 0x00040000U #define MAC_PCU_STA_ADDR_U16__PW_SAVE__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_PCU_STA_ADDR_U16__PW_SAVE__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_PCU_STA_ADDR_U16__PW_SAVE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_PCU_STA_ADDR_U16__PW_SAVE__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_PCU_STA_ADDR_U16__PW_SAVE__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field KEYSRCH_DIS */ #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SHIFT 19 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MASK 0x00080000U #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field PCF */ #define MAC_PCU_STA_ADDR_U16__PCF__SHIFT 20 #define MAC_PCU_STA_ADDR_U16__PCF__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__PCF__MASK 0x00100000U #define MAC_PCU_STA_ADDR_U16__PCF__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_STA_ADDR_U16__PCF__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_STA_ADDR_U16__PCF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_STA_ADDR_U16__PCF__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_STA_ADDR_U16__PCF__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field USE_DEFANT */ #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SHIFT 21 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MASK 0x00200000U #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field DEFANT_UPDATE */ #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SHIFT 22 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MASK 0x00400000U #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field RTS_USE_DEF */ #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SHIFT 23 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MASK 0x00800000U #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field ACKCTS_6MB */ #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SHIFT 24 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MASK 0x01000000U #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field BASE_RATE_11B */ #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SHIFT 25 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MASK 0x02000000U #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) /* macros for field SECTOR_SELF_GEN */ #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SHIFT 26 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MASK 0x04000000U #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__READ(src) \ (((u_int32_t)(src)\ & 0x04000000U) >> 26) #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WRITE(src) \ (((u_int32_t)(src)\ << 26) & 0x04000000U) #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x04000000U) | (((u_int32_t)(src) <<\ 26) & 0x04000000U) #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 26) & ~0x04000000U))) #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SET(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(1) << 26) #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__CLR(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(0) << 26) /* macros for field CRPT_MIC_ENABLE */ #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SHIFT 27 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MASK 0x08000000U #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field KSRCH_MODE */ #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SHIFT 28 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MASK 0x10000000U #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field PRESERVE_SEQNUM */ #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SHIFT 29 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MASK 0x20000000U #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field CBCIV_ENDIAN */ #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SHIFT 30 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MASK 0x40000000U #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) /* macros for field ADHOC_MCAST_SEARCH */ #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SHIFT 31 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WIDTH 1 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MASK 0x80000000U #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define MAC_PCU_STA_ADDR_U16__TYPE u_int32_t #define MAC_PCU_STA_ADDR_U16__READ 0xffffffffU #define MAC_PCU_STA_ADDR_U16__WRITE 0xffffffffU #endif /* __MAC_PCU_STA_ADDR_U16_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_U16 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_U16__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_L32 */ #ifndef __MAC_PCU_BSSID_L32_MACRO__ #define __MAC_PCU_BSSID_L32_MACRO__ /* macros for field ADDR */ #define MAC_PCU_BSSID_L32__ADDR__SHIFT 0 #define MAC_PCU_BSSID_L32__ADDR__WIDTH 32 #define MAC_PCU_BSSID_L32__ADDR__MASK 0xffffffffU #define MAC_PCU_BSSID_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_BSSID_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BSSID_L32__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BSSID_L32__TYPE u_int32_t #define MAC_PCU_BSSID_L32__READ 0xffffffffU #define MAC_PCU_BSSID_L32__WRITE 0xffffffffU #endif /* __MAC_PCU_BSSID_L32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BSSID_L32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_L32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_U16 */ #ifndef __MAC_PCU_BSSID_U16_MACRO__ #define __MAC_PCU_BSSID_U16_MACRO__ /* macros for field ADDR */ #define MAC_PCU_BSSID_U16__ADDR__SHIFT 0 #define MAC_PCU_BSSID_U16__ADDR__WIDTH 16 #define MAC_PCU_BSSID_U16__ADDR__MASK 0x0000ffffU #define MAC_PCU_BSSID_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_BSSID_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_BSSID_U16__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field AID */ #define MAC_PCU_BSSID_U16__AID__SHIFT 16 #define MAC_PCU_BSSID_U16__AID__WIDTH 11 #define MAC_PCU_BSSID_U16__AID__MASK 0x07ff0000U #define MAC_PCU_BSSID_U16__AID__READ(src) \ (((u_int32_t)(src)\ & 0x07ff0000U) >> 16) #define MAC_PCU_BSSID_U16__AID__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x07ff0000U) #define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x07ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x07ff0000U) #define MAC_PCU_BSSID_U16__AID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x07ff0000U))) #define MAC_PCU_BSSID_U16__TYPE u_int32_t #define MAC_PCU_BSSID_U16__READ 0x07ffffffU #define MAC_PCU_BSSID_U16__WRITE 0x07ffffffU #endif /* __MAC_PCU_BSSID_U16_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BSSID_U16 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_U16__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_AVE */ #ifndef __MAC_PCU_BCN_RSSI_AVE_MACRO__ #define __MAC_PCU_BCN_RSSI_AVE_MACRO__ /* macros for field AVE_VALUE */ #define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__SHIFT 0 #define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__WIDTH 12 #define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__MASK 0x00000fffU #define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__READ(src) \ (u_int32_t)(src)\ & 0x00000fffU /* macros for field SPARE */ #define MAC_PCU_BCN_RSSI_AVE__SPARE__SHIFT 12 #define MAC_PCU_BCN_RSSI_AVE__SPARE__WIDTH 8 #define MAC_PCU_BCN_RSSI_AVE__SPARE__MASK 0x000ff000U #define MAC_PCU_BCN_RSSI_AVE__SPARE__READ(src) \ (((u_int32_t)(src)\ & 0x000ff000U) >> 12) #define MAC_PCU_BCN_RSSI_AVE__SPARE__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x000ff000U) #define MAC_PCU_BCN_RSSI_AVE__SPARE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000ff000U) | (((u_int32_t)(src) <<\ 12) & 0x000ff000U) #define MAC_PCU_BCN_RSSI_AVE__SPARE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x000ff000U))) #define MAC_PCU_BCN_RSSI_AVE__TYPE u_int32_t #define MAC_PCU_BCN_RSSI_AVE__READ 0x000fffffU #define MAC_PCU_BCN_RSSI_AVE__WRITE 0x000fffffU #endif /* __MAC_PCU_BCN_RSSI_AVE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_AVE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_AVE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_CTS_TIMEOUT */ #ifndef __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ #define __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ /* macros for field ACK_TIMEOUT */ #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__SHIFT 0 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WIDTH 14 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MASK 0x00003fffU #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__READ(src) \ (u_int32_t)(src)\ & 0x00003fffU #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WRITE(src) \ ((u_int32_t)(src)\ & 0x00003fffU) #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00003fffU) | ((u_int32_t)(src) &\ 0x00003fffU) #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00003fffU))) /* macros for field CTS_TIMEOUT */ #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__SHIFT 16 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WIDTH 14 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MASK 0x3fff0000U #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__READ(src) \ (((u_int32_t)(src)\ & 0x3fff0000U) >> 16) #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x3fff0000U) #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x3fff0000U) | (((u_int32_t)(src) <<\ 16) & 0x3fff0000U) #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x3fff0000U))) #define MAC_PCU_ACK_CTS_TIMEOUT__TYPE u_int32_t #define MAC_PCU_ACK_CTS_TIMEOUT__READ 0x3fff3fffU #define MAC_PCU_ACK_CTS_TIMEOUT__WRITE 0x3fff3fffU #endif /* __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_ACK_CTS_TIMEOUT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_CTS_TIMEOUT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_CTL */ #ifndef __MAC_PCU_BCN_RSSI_CTL_MACRO__ #define __MAC_PCU_BCN_RSSI_CTL_MACRO__ /* macros for field RSSI_THRESH */ #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__SHIFT 0 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WIDTH 8 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MASK 0x000000ffU #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field MISS_THRESH */ #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__SHIFT 8 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WIDTH 8 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MASK 0x0000ff00U #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field WEIGHT */ #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__SHIFT 24 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WIDTH 5 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MASK 0x1f000000U #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__READ(src) \ (((u_int32_t)(src)\ & 0x1f000000U) >> 24) #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x1f000000U) #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x1f000000U) | (((u_int32_t)(src) <<\ 24) & 0x1f000000U) #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x1f000000U))) /* macros for field RESET */ #define MAC_PCU_BCN_RSSI_CTL__RESET__SHIFT 29 #define MAC_PCU_BCN_RSSI_CTL__RESET__WIDTH 1 #define MAC_PCU_BCN_RSSI_CTL__RESET__MASK 0x20000000U #define MAC_PCU_BCN_RSSI_CTL__RESET__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_PCU_BCN_RSSI_CTL__RESET__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define MAC_PCU_BCN_RSSI_CTL__RESET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define MAC_PCU_BCN_RSSI_CTL__RESET__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_PCU_BCN_RSSI_CTL__RESET__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) #define MAC_PCU_BCN_RSSI_CTL__TYPE u_int32_t #define MAC_PCU_BCN_RSSI_CTL__READ 0x3f00ffffU #define MAC_PCU_BCN_RSSI_CTL__WRITE 0x3f00ffffU #endif /* __MAC_PCU_BCN_RSSI_CTL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_CTL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_CTL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_USEC_LATENCY */ #ifndef __MAC_PCU_USEC_LATENCY_MACRO__ #define __MAC_PCU_USEC_LATENCY_MACRO__ /* macros for field USEC */ #define MAC_PCU_USEC_LATENCY__USEC__SHIFT 0 #define MAC_PCU_USEC_LATENCY__USEC__WIDTH 8 #define MAC_PCU_USEC_LATENCY__USEC__MASK 0x000000ffU #define MAC_PCU_USEC_LATENCY__USEC__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_USEC_LATENCY__USEC__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_USEC_LATENCY__USEC__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field TX_LATENCY */ #define MAC_PCU_USEC_LATENCY__TX_LATENCY__SHIFT 14 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__WIDTH 9 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__MASK 0x007fc000U #define MAC_PCU_USEC_LATENCY__TX_LATENCY__READ(src) \ (((u_int32_t)(src)\ & 0x007fc000U) >> 14) #define MAC_PCU_USEC_LATENCY__TX_LATENCY__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x007fc000U) #define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x007fc000U) | (((u_int32_t)(src) <<\ 14) & 0x007fc000U) #define MAC_PCU_USEC_LATENCY__TX_LATENCY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x007fc000U))) /* macros for field RX_LATENCY */ #define MAC_PCU_USEC_LATENCY__RX_LATENCY__SHIFT 23 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__WIDTH 6 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__MASK 0x1f800000U #define MAC_PCU_USEC_LATENCY__RX_LATENCY__READ(src) \ (((u_int32_t)(src)\ & 0x1f800000U) >> 23) #define MAC_PCU_USEC_LATENCY__RX_LATENCY__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x1f800000U) #define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x1f800000U) | (((u_int32_t)(src) <<\ 23) & 0x1f800000U) #define MAC_PCU_USEC_LATENCY__RX_LATENCY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x1f800000U))) #define MAC_PCU_USEC_LATENCY__TYPE u_int32_t #define MAC_PCU_USEC_LATENCY__READ 0x1fffc0ffU #define MAC_PCU_USEC_LATENCY__WRITE 0x1fffc0ffU #endif /* __MAC_PCU_USEC_LATENCY_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_USEC_LATENCY */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_USEC_LATENCY__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RESET_TSF */ #ifndef __MAC_PCU_RESET_TSF_MACRO__ #define __MAC_PCU_RESET_TSF_MACRO__ /* macros for field ONE_SHOT */ #define MAC_PCU_RESET_TSF__ONE_SHOT__SHIFT 24 #define MAC_PCU_RESET_TSF__ONE_SHOT__WIDTH 1 #define MAC_PCU_RESET_TSF__ONE_SHOT__MASK 0x01000000U #define MAC_PCU_RESET_TSF__ONE_SHOT__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_RESET_TSF__ONE_SHOT__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_PCU_RESET_TSF__ONE_SHOT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_PCU_RESET_TSF__ONE_SHOT__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_RESET_TSF__ONE_SHOT__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field ONE_SHOT2 */ #define MAC_PCU_RESET_TSF__ONE_SHOT2__SHIFT 25 #define MAC_PCU_RESET_TSF__ONE_SHOT2__WIDTH 1 #define MAC_PCU_RESET_TSF__ONE_SHOT2__MASK 0x02000000U #define MAC_PCU_RESET_TSF__ONE_SHOT2__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_RESET_TSF__ONE_SHOT2__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_RESET_TSF__ONE_SHOT2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_RESET_TSF__ONE_SHOT2__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_RESET_TSF__ONE_SHOT2__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) #define MAC_PCU_RESET_TSF__TYPE u_int32_t #define MAC_PCU_RESET_TSF__READ 0x03000000U #define MAC_PCU_RESET_TSF__WRITE 0x03000000U #endif /* __MAC_PCU_RESET_TSF_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RESET_TSF */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RESET_TSF__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MAX_CFP_DUR */ #ifndef __MAC_PCU_MAX_CFP_DUR_MACRO__ #define __MAC_PCU_MAX_CFP_DUR_MACRO__ /* macros for field VALUE */ #define MAC_PCU_MAX_CFP_DUR__VALUE__SHIFT 0 #define MAC_PCU_MAX_CFP_DUR__VALUE__WIDTH 16 #define MAC_PCU_MAX_CFP_DUR__VALUE__MASK 0x0000ffffU #define MAC_PCU_MAX_CFP_DUR__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_MAX_CFP_DUR__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_MAX_CFP_DUR__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field USEC_FRAC_NUMERATOR */ #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__SHIFT 16 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WIDTH 4 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MASK 0x000f0000U #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__READ(src) \ (((u_int32_t)(src)\ & 0x000f0000U) >> 16) #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x000f0000U) #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000f0000U) | (((u_int32_t)(src) <<\ 16) & 0x000f0000U) #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x000f0000U))) /* macros for field USEC_FRAC_DENOMINATOR */ #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__SHIFT 24 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WIDTH 4 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MASK 0x0f000000U #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__READ(src) \ (((u_int32_t)(src)\ & 0x0f000000U) >> 24) #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x0f000000U) #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0f000000U) | (((u_int32_t)(src) <<\ 24) & 0x0f000000U) #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x0f000000U))) #define MAC_PCU_MAX_CFP_DUR__TYPE u_int32_t #define MAC_PCU_MAX_CFP_DUR__READ 0x0f0fffffU #define MAC_PCU_MAX_CFP_DUR__WRITE 0x0f0fffffU #endif /* __MAC_PCU_MAX_CFP_DUR_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MAX_CFP_DUR */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MAX_CFP_DUR__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FILTER */ #ifndef __MAC_PCU_RX_FILTER_MACRO__ #define __MAC_PCU_RX_FILTER_MACRO__ /* macros for field UNICAST */ #define MAC_PCU_RX_FILTER__UNICAST__SHIFT 0 #define MAC_PCU_RX_FILTER__UNICAST__WIDTH 1 #define MAC_PCU_RX_FILTER__UNICAST__MASK 0x00000001U #define MAC_PCU_RX_FILTER__UNICAST__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_RX_FILTER__UNICAST__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_RX_FILTER__UNICAST__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_RX_FILTER__UNICAST__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_RX_FILTER__UNICAST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field MULTICAST */ #define MAC_PCU_RX_FILTER__MULTICAST__SHIFT 1 #define MAC_PCU_RX_FILTER__MULTICAST__WIDTH 1 #define MAC_PCU_RX_FILTER__MULTICAST__MASK 0x00000002U #define MAC_PCU_RX_FILTER__MULTICAST__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_RX_FILTER__MULTICAST__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_RX_FILTER__MULTICAST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_RX_FILTER__MULTICAST__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_RX_FILTER__MULTICAST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field BROADCAST */ #define MAC_PCU_RX_FILTER__BROADCAST__SHIFT 2 #define MAC_PCU_RX_FILTER__BROADCAST__WIDTH 1 #define MAC_PCU_RX_FILTER__BROADCAST__MASK 0x00000004U #define MAC_PCU_RX_FILTER__BROADCAST__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_RX_FILTER__BROADCAST__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_RX_FILTER__BROADCAST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_RX_FILTER__BROADCAST__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_RX_FILTER__BROADCAST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field CONTROL */ #define MAC_PCU_RX_FILTER__CONTROL__SHIFT 3 #define MAC_PCU_RX_FILTER__CONTROL__WIDTH 1 #define MAC_PCU_RX_FILTER__CONTROL__MASK 0x00000008U #define MAC_PCU_RX_FILTER__CONTROL__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_RX_FILTER__CONTROL__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_RX_FILTER__CONTROL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_RX_FILTER__CONTROL__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_RX_FILTER__CONTROL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field BEACON */ #define MAC_PCU_RX_FILTER__BEACON__SHIFT 4 #define MAC_PCU_RX_FILTER__BEACON__WIDTH 1 #define MAC_PCU_RX_FILTER__BEACON__MASK 0x00000010U #define MAC_PCU_RX_FILTER__BEACON__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_RX_FILTER__BEACON__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_RX_FILTER__BEACON__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_RX_FILTER__BEACON__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_RX_FILTER__BEACON__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field PROMISCUOUS */ #define MAC_PCU_RX_FILTER__PROMISCUOUS__SHIFT 5 #define MAC_PCU_RX_FILTER__PROMISCUOUS__WIDTH 1 #define MAC_PCU_RX_FILTER__PROMISCUOUS__MASK 0x00000020U #define MAC_PCU_RX_FILTER__PROMISCUOUS__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_RX_FILTER__PROMISCUOUS__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_RX_FILTER__PROMISCUOUS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_RX_FILTER__PROMISCUOUS__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_RX_FILTER__PROMISCUOUS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field XR_POLL */ #define MAC_PCU_RX_FILTER__XR_POLL__SHIFT 6 #define MAC_PCU_RX_FILTER__XR_POLL__WIDTH 1 #define MAC_PCU_RX_FILTER__XR_POLL__MASK 0x00000040U #define MAC_PCU_RX_FILTER__XR_POLL__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_RX_FILTER__XR_POLL__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_RX_FILTER__XR_POLL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_RX_FILTER__XR_POLL__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_RX_FILTER__XR_POLL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field PROBE_REQ */ #define MAC_PCU_RX_FILTER__PROBE_REQ__SHIFT 7 #define MAC_PCU_RX_FILTER__PROBE_REQ__WIDTH 1 #define MAC_PCU_RX_FILTER__PROBE_REQ__MASK 0x00000080U #define MAC_PCU_RX_FILTER__PROBE_REQ__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_RX_FILTER__PROBE_REQ__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_RX_FILTER__PROBE_REQ__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_RX_FILTER__PROBE_REQ__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_RX_FILTER__PROBE_REQ__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field SYNC_FRAME */ #define MAC_PCU_RX_FILTER__SYNC_FRAME__SHIFT 8 #define MAC_PCU_RX_FILTER__SYNC_FRAME__WIDTH 1 #define MAC_PCU_RX_FILTER__SYNC_FRAME__MASK 0x00000100U #define MAC_PCU_RX_FILTER__SYNC_FRAME__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_RX_FILTER__SYNC_FRAME__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_PCU_RX_FILTER__SYNC_FRAME__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_PCU_RX_FILTER__SYNC_FRAME__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_RX_FILTER__SYNC_FRAME__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field MY_BEACON */ #define MAC_PCU_RX_FILTER__MY_BEACON__SHIFT 9 #define MAC_PCU_RX_FILTER__MY_BEACON__WIDTH 1 #define MAC_PCU_RX_FILTER__MY_BEACON__MASK 0x00000200U #define MAC_PCU_RX_FILTER__MY_BEACON__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_PCU_RX_FILTER__MY_BEACON__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_PCU_RX_FILTER__MY_BEACON__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_PCU_RX_FILTER__MY_BEACON__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_PCU_RX_FILTER__MY_BEACON__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field COMPRESSED_BAR */ #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SHIFT 10 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WIDTH 1 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MASK 0x00000400U #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field COMPRESSED_BA */ #define MAC_PCU_RX_FILTER__COMPRESSED_BA__SHIFT 11 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__WIDTH 1 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__MASK 0x00000800U #define MAC_PCU_RX_FILTER__COMPRESSED_BA__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_RX_FILTER__COMPRESSED_BA__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_PCU_RX_FILTER__COMPRESSED_BA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_PCU_RX_FILTER__COMPRESSED_BA__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_RX_FILTER__COMPRESSED_BA__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field UNCOMPRESSED_BA_BAR */ #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SHIFT 12 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WIDTH 1 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MASK 0x00001000U #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field ASSUME_RADAR */ #define MAC_PCU_RX_FILTER__ASSUME_RADAR__SHIFT 13 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__WIDTH 1 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__MASK 0x00002000U #define MAC_PCU_RX_FILTER__ASSUME_RADAR__READ(src) \ (((u_int32_t)(src)\ & 0x00002000U) >> 13) #define MAC_PCU_RX_FILTER__ASSUME_RADAR__WRITE(src) \ (((u_int32_t)(src)\ << 13) & 0x00002000U) #define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00002000U) | (((u_int32_t)(src) <<\ 13) & 0x00002000U) #define MAC_PCU_RX_FILTER__ASSUME_RADAR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 13) & ~0x00002000U))) #define MAC_PCU_RX_FILTER__ASSUME_RADAR__SET(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(1) << 13) #define MAC_PCU_RX_FILTER__ASSUME_RADAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(0) << 13) /* macros for field PS_POLL */ #define MAC_PCU_RX_FILTER__PS_POLL__SHIFT 14 #define MAC_PCU_RX_FILTER__PS_POLL__WIDTH 1 #define MAC_PCU_RX_FILTER__PS_POLL__MASK 0x00004000U #define MAC_PCU_RX_FILTER__PS_POLL__READ(src) \ (((u_int32_t)(src)\ & 0x00004000U) >> 14) #define MAC_PCU_RX_FILTER__PS_POLL__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x00004000U) #define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00004000U) | (((u_int32_t)(src) <<\ 14) & 0x00004000U) #define MAC_PCU_RX_FILTER__PS_POLL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x00004000U))) #define MAC_PCU_RX_FILTER__PS_POLL__SET(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(1) << 14) #define MAC_PCU_RX_FILTER__PS_POLL__CLR(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(0) << 14) /* macros for field MCAST_BCAST_ALL */ #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SHIFT 15 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WIDTH 1 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MASK 0x00008000U #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__READ(src) \ (((u_int32_t)(src)\ & 0x00008000U) >> 15) #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WRITE(src) \ (((u_int32_t)(src)\ << 15) & 0x00008000U) #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00008000U) | (((u_int32_t)(src) <<\ 15) & 0x00008000U) #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 15) & ~0x00008000U))) #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SET(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(1) << 15) #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__CLR(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(0) << 15) /* macros for field RST_DLMTR_CNT_DISABLE */ #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SHIFT 16 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WIDTH 1 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MASK 0x00010000U #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field HW_BCN_PROC_ENABLE */ #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SHIFT 17 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WIDTH 1 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MASK 0x00020000U #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field MGMT_ACTION_MCAST */ #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SHIFT 18 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WIDTH 1 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MASK 0x00040000U #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field CONTROL_WRAPPER */ #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SHIFT 19 #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WIDTH 1 #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MASK 0x00080000U #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field FROM_TO_DS */ #define MAC_PCU_RX_FILTER__FROM_TO_DS__SHIFT 20 #define MAC_PCU_RX_FILTER__FROM_TO_DS__WIDTH 1 #define MAC_PCU_RX_FILTER__FROM_TO_DS__MASK 0x00100000U #define MAC_PCU_RX_FILTER__FROM_TO_DS__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_RX_FILTER__FROM_TO_DS__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_RX_FILTER__FROM_TO_DS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_RX_FILTER__FROM_TO_DS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_RX_FILTER__FROM_TO_DS__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_RX_FILTER__FROM_TO_DS__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) #define MAC_PCU_RX_FILTER__TYPE u_int32_t #define MAC_PCU_RX_FILTER__READ 0x001fffffU #define MAC_PCU_RX_FILTER__WRITE 0x001fffffU #endif /* __MAC_PCU_RX_FILTER_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RX_FILTER */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FILTER__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_L32 */ #ifndef __MAC_PCU_MCAST_FILTER_L32_MACRO__ #define __MAC_PCU_MCAST_FILTER_L32_MACRO__ /* macros for field VALUE */ #define MAC_PCU_MCAST_FILTER_L32__VALUE__SHIFT 0 #define MAC_PCU_MCAST_FILTER_L32__VALUE__WIDTH 32 #define MAC_PCU_MCAST_FILTER_L32__VALUE__MASK 0xffffffffU #define MAC_PCU_MCAST_FILTER_L32__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_MCAST_FILTER_L32__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_MCAST_FILTER_L32__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_MCAST_FILTER_L32__TYPE u_int32_t #define MAC_PCU_MCAST_FILTER_L32__READ 0xffffffffU #define MAC_PCU_MCAST_FILTER_L32__WRITE 0xffffffffU #endif /* __MAC_PCU_MCAST_FILTER_L32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_L32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_L32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_U32 */ #ifndef __MAC_PCU_MCAST_FILTER_U32_MACRO__ #define __MAC_PCU_MCAST_FILTER_U32_MACRO__ /* macros for field VALUE */ #define MAC_PCU_MCAST_FILTER_U32__VALUE__SHIFT 0 #define MAC_PCU_MCAST_FILTER_U32__VALUE__WIDTH 32 #define MAC_PCU_MCAST_FILTER_U32__VALUE__MASK 0xffffffffU #define MAC_PCU_MCAST_FILTER_U32__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_MCAST_FILTER_U32__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_MCAST_FILTER_U32__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_MCAST_FILTER_U32__TYPE u_int32_t #define MAC_PCU_MCAST_FILTER_U32__READ 0xffffffffU #define MAC_PCU_MCAST_FILTER_U32__WRITE 0xffffffffU #endif /* __MAC_PCU_MCAST_FILTER_U32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_U32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_U32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_DIAG_SW */ #ifndef __MAC_PCU_DIAG_SW_MACRO__ #define __MAC_PCU_DIAG_SW_MACRO__ /* macros for field INVALID_KEY_NO_ACK */ #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SHIFT 0 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WIDTH 1 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MASK 0x00000001U #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field NO_ACK */ #define MAC_PCU_DIAG_SW__NO_ACK__SHIFT 1 #define MAC_PCU_DIAG_SW__NO_ACK__WIDTH 1 #define MAC_PCU_DIAG_SW__NO_ACK__MASK 0x00000002U #define MAC_PCU_DIAG_SW__NO_ACK__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_DIAG_SW__NO_ACK__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_DIAG_SW__NO_ACK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_DIAG_SW__NO_ACK__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_DIAG_SW__NO_ACK__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field NO_CTS */ #define MAC_PCU_DIAG_SW__NO_CTS__SHIFT 2 #define MAC_PCU_DIAG_SW__NO_CTS__WIDTH 1 #define MAC_PCU_DIAG_SW__NO_CTS__MASK 0x00000004U #define MAC_PCU_DIAG_SW__NO_CTS__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_DIAG_SW__NO_CTS__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_DIAG_SW__NO_CTS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_DIAG_SW__NO_CTS__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_DIAG_SW__NO_CTS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field NO_ENCRYPT */ #define MAC_PCU_DIAG_SW__NO_ENCRYPT__SHIFT 3 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__WIDTH 1 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__MASK 0x00000008U #define MAC_PCU_DIAG_SW__NO_ENCRYPT__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_DIAG_SW__NO_ENCRYPT__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_DIAG_SW__NO_ENCRYPT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_DIAG_SW__NO_ENCRYPT__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_DIAG_SW__NO_ENCRYPT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field NO_DECRYPT */ #define MAC_PCU_DIAG_SW__NO_DECRYPT__SHIFT 4 #define MAC_PCU_DIAG_SW__NO_DECRYPT__WIDTH 1 #define MAC_PCU_DIAG_SW__NO_DECRYPT__MASK 0x00000010U #define MAC_PCU_DIAG_SW__NO_DECRYPT__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_DIAG_SW__NO_DECRYPT__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_DIAG_SW__NO_DECRYPT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_DIAG_SW__NO_DECRYPT__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_DIAG_SW__NO_DECRYPT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field HALT_RX */ #define MAC_PCU_DIAG_SW__HALT_RX__SHIFT 5 #define MAC_PCU_DIAG_SW__HALT_RX__WIDTH 1 #define MAC_PCU_DIAG_SW__HALT_RX__MASK 0x00000020U #define MAC_PCU_DIAG_SW__HALT_RX__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_DIAG_SW__HALT_RX__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_DIAG_SW__HALT_RX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_DIAG_SW__HALT_RX__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_DIAG_SW__HALT_RX__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field LOOP_BACK */ #define MAC_PCU_DIAG_SW__LOOP_BACK__SHIFT 6 #define MAC_PCU_DIAG_SW__LOOP_BACK__WIDTH 1 #define MAC_PCU_DIAG_SW__LOOP_BACK__MASK 0x00000040U #define MAC_PCU_DIAG_SW__LOOP_BACK__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_DIAG_SW__LOOP_BACK__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_DIAG_SW__LOOP_BACK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_DIAG_SW__LOOP_BACK__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_DIAG_SW__LOOP_BACK__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field CORRUPT_FCS */ #define MAC_PCU_DIAG_SW__CORRUPT_FCS__SHIFT 7 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__WIDTH 1 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__MASK 0x00000080U #define MAC_PCU_DIAG_SW__CORRUPT_FCS__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_DIAG_SW__CORRUPT_FCS__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_DIAG_SW__CORRUPT_FCS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_DIAG_SW__CORRUPT_FCS__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_DIAG_SW__CORRUPT_FCS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field DUMP_CHAN_INFO */ #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SHIFT 8 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WIDTH 1 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MASK 0x00000100U #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field ACCEPT_NON_V0 */ #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SHIFT 17 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WIDTH 1 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MASK 0x00020000U #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field OBS_SEL_1_0 */ #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__SHIFT 18 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WIDTH 2 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MASK 0x000c0000U #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__READ(src) \ (((u_int32_t)(src)\ & 0x000c0000U) >> 18) #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x000c0000U) #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000c0000U) | (((u_int32_t)(src) <<\ 18) & 0x000c0000U) #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x000c0000U))) /* macros for field RX_CLEAR_HIGH */ #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SHIFT 20 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WIDTH 1 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MASK 0x00100000U #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field IGNORE_NAV */ #define MAC_PCU_DIAG_SW__IGNORE_NAV__SHIFT 21 #define MAC_PCU_DIAG_SW__IGNORE_NAV__WIDTH 1 #define MAC_PCU_DIAG_SW__IGNORE_NAV__MASK 0x00200000U #define MAC_PCU_DIAG_SW__IGNORE_NAV__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_DIAG_SW__IGNORE_NAV__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_PCU_DIAG_SW__IGNORE_NAV__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_PCU_DIAG_SW__IGNORE_NAV__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_DIAG_SW__IGNORE_NAV__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field CHAN_IDLE_HIGH */ #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SHIFT 22 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WIDTH 1 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MASK 0x00400000U #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field PHYERR_ENABLE_EIFS_CTL */ #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SHIFT 23 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WIDTH 1 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MASK 0x00800000U #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field DUAL_CHAIN_CHAN_INFO */ #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SHIFT 24 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WIDTH 1 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MASK 0x01000000U #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field FORCE_RX_ABORT */ #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SHIFT 25 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WIDTH 1 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MASK 0x02000000U #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) /* macros for field SATURATE_CYCLE_CNT */ #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SHIFT 26 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WIDTH 1 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MASK 0x04000000U #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__READ(src) \ (((u_int32_t)(src)\ & 0x04000000U) >> 26) #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WRITE(src) \ (((u_int32_t)(src)\ << 26) & 0x04000000U) #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x04000000U) | (((u_int32_t)(src) <<\ 26) & 0x04000000U) #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 26) & ~0x04000000U))) #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SET(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(1) << 26) #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__CLR(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(0) << 26) /* macros for field OBS_SEL_2 */ #define MAC_PCU_DIAG_SW__OBS_SEL_2__SHIFT 27 #define MAC_PCU_DIAG_SW__OBS_SEL_2__WIDTH 1 #define MAC_PCU_DIAG_SW__OBS_SEL_2__MASK 0x08000000U #define MAC_PCU_DIAG_SW__OBS_SEL_2__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define MAC_PCU_DIAG_SW__OBS_SEL_2__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define MAC_PCU_DIAG_SW__OBS_SEL_2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define MAC_PCU_DIAG_SW__OBS_SEL_2__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define MAC_PCU_DIAG_SW__OBS_SEL_2__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field RX_CLEAR_CTL_LOW */ #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SHIFT 28 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WIDTH 1 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MASK 0x10000000U #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field RX_CLEAR_EXT_LOW */ #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SHIFT 29 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WIDTH 1 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MASK 0x20000000U #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field DEBUG_MODE */ #define MAC_PCU_DIAG_SW__DEBUG_MODE__SHIFT 30 #define MAC_PCU_DIAG_SW__DEBUG_MODE__WIDTH 2 #define MAC_PCU_DIAG_SW__DEBUG_MODE__MASK 0xc0000000U #define MAC_PCU_DIAG_SW__DEBUG_MODE__READ(src) \ (((u_int32_t)(src)\ & 0xc0000000U) >> 30) #define MAC_PCU_DIAG_SW__DEBUG_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0xc0000000U) #define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xc0000000U) | (((u_int32_t)(src) <<\ 30) & 0xc0000000U) #define MAC_PCU_DIAG_SW__DEBUG_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0xc0000000U))) #define MAC_PCU_DIAG_SW__TYPE u_int32_t #define MAC_PCU_DIAG_SW__READ 0xfffe01ffU #define MAC_PCU_DIAG_SW__WRITE 0xfffe01ffU #endif /* __MAC_PCU_DIAG_SW_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_DIAG_SW */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_DIAG_SW__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_L32 */ #ifndef __MAC_PCU_TSF_L32_MACRO__ #define __MAC_PCU_TSF_L32_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TSF_L32__VALUE__SHIFT 0 #define MAC_PCU_TSF_L32__VALUE__WIDTH 32 #define MAC_PCU_TSF_L32__VALUE__MASK 0xffffffffU #define MAC_PCU_TSF_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TSF_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TSF_L32__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TSF_L32__TYPE u_int32_t #define MAC_PCU_TSF_L32__READ 0xffffffffU #define MAC_PCU_TSF_L32__WRITE 0xffffffffU #endif /* __MAC_PCU_TSF_L32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TSF_L32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_L32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_U32 */ #ifndef __MAC_PCU_TSF_U32_MACRO__ #define __MAC_PCU_TSF_U32_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TSF_U32__VALUE__SHIFT 0 #define MAC_PCU_TSF_U32__VALUE__WIDTH 32 #define MAC_PCU_TSF_U32__VALUE__MASK 0xffffffffU #define MAC_PCU_TSF_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TSF_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TSF_U32__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TSF_U32__TYPE u_int32_t #define MAC_PCU_TSF_U32__READ 0xffffffffU #define MAC_PCU_TSF_U32__WRITE 0xffffffffU #endif /* __MAC_PCU_TSF_U32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TSF_U32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_U32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TST_ADDAC */ #ifndef __MAC_PCU_TST_ADDAC_MACRO__ #define __MAC_PCU_TST_ADDAC_MACRO__ /* macros for field CONT_TX */ #define MAC_PCU_TST_ADDAC__CONT_TX__SHIFT 0 #define MAC_PCU_TST_ADDAC__CONT_TX__WIDTH 1 #define MAC_PCU_TST_ADDAC__CONT_TX__MASK 0x00000001U #define MAC_PCU_TST_ADDAC__CONT_TX__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_TST_ADDAC__CONT_TX__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_TST_ADDAC__CONT_TX__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_TST_ADDAC__CONT_TX__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_TST_ADDAC__CONT_TX__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field TESTMODE */ #define MAC_PCU_TST_ADDAC__TESTMODE__SHIFT 1 #define MAC_PCU_TST_ADDAC__TESTMODE__WIDTH 1 #define MAC_PCU_TST_ADDAC__TESTMODE__MASK 0x00000002U #define MAC_PCU_TST_ADDAC__TESTMODE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_TST_ADDAC__TESTMODE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_TST_ADDAC__TESTMODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_TST_ADDAC__TESTMODE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_TST_ADDAC__TESTMODE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field LOOP */ #define MAC_PCU_TST_ADDAC__LOOP__SHIFT 2 #define MAC_PCU_TST_ADDAC__LOOP__WIDTH 1 #define MAC_PCU_TST_ADDAC__LOOP__MASK 0x00000004U #define MAC_PCU_TST_ADDAC__LOOP__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_TST_ADDAC__LOOP__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_TST_ADDAC__LOOP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_TST_ADDAC__LOOP__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_TST_ADDAC__LOOP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field LOOP_LEN */ #define MAC_PCU_TST_ADDAC__LOOP_LEN__SHIFT 3 #define MAC_PCU_TST_ADDAC__LOOP_LEN__WIDTH 11 #define MAC_PCU_TST_ADDAC__LOOP_LEN__MASK 0x00003ff8U #define MAC_PCU_TST_ADDAC__LOOP_LEN__READ(src) \ (((u_int32_t)(src)\ & 0x00003ff8U) >> 3) #define MAC_PCU_TST_ADDAC__LOOP_LEN__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00003ff8U) #define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00003ff8U) | (((u_int32_t)(src) <<\ 3) & 0x00003ff8U) #define MAC_PCU_TST_ADDAC__LOOP_LEN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00003ff8U))) /* macros for field UPPER_8B */ #define MAC_PCU_TST_ADDAC__UPPER_8B__SHIFT 14 #define MAC_PCU_TST_ADDAC__UPPER_8B__WIDTH 1 #define MAC_PCU_TST_ADDAC__UPPER_8B__MASK 0x00004000U #define MAC_PCU_TST_ADDAC__UPPER_8B__READ(src) \ (((u_int32_t)(src)\ & 0x00004000U) >> 14) #define MAC_PCU_TST_ADDAC__UPPER_8B__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x00004000U) #define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00004000U) | (((u_int32_t)(src) <<\ 14) & 0x00004000U) #define MAC_PCU_TST_ADDAC__UPPER_8B__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x00004000U))) #define MAC_PCU_TST_ADDAC__UPPER_8B__SET(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(1) << 14) #define MAC_PCU_TST_ADDAC__UPPER_8B__CLR(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(0) << 14) /* macros for field SAMPLE_SIZE_2K */ #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SHIFT 15 #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WIDTH 1 #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MASK 0x00008000U #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__READ(src) \ (((u_int32_t)(src)\ & 0x00008000U) >> 15) #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WRITE(src) \ (((u_int32_t)(src)\ << 15) & 0x00008000U) #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00008000U) | (((u_int32_t)(src) <<\ 15) & 0x00008000U) #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__VERIFY(src) \ (!((((u_int32_t)(src)\ << 15) & ~0x00008000U))) #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SET(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(1) << 15) #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__CLR(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(0) << 15) /* macros for field TRIG_SEL */ #define MAC_PCU_TST_ADDAC__TRIG_SEL__SHIFT 16 #define MAC_PCU_TST_ADDAC__TRIG_SEL__WIDTH 1 #define MAC_PCU_TST_ADDAC__TRIG_SEL__MASK 0x00010000U #define MAC_PCU_TST_ADDAC__TRIG_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_TST_ADDAC__TRIG_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_TST_ADDAC__TRIG_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_TST_ADDAC__TRIG_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_TST_ADDAC__TRIG_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field TRIG_POLARITY */ #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SHIFT 17 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WIDTH 1 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MASK 0x00020000U #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field CONT_TEST */ #define MAC_PCU_TST_ADDAC__CONT_TEST__SHIFT 18 #define MAC_PCU_TST_ADDAC__CONT_TEST__WIDTH 1 #define MAC_PCU_TST_ADDAC__CONT_TEST__MASK 0x00040000U #define MAC_PCU_TST_ADDAC__CONT_TEST__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_PCU_TST_ADDAC__CONT_TEST__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_PCU_TST_ADDAC__CONT_TEST__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field TEST_CAPTURE */ #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SHIFT 19 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WIDTH 1 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MASK 0x00080000U #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field TEST_ARM */ #define MAC_PCU_TST_ADDAC__TEST_ARM__SHIFT 20 #define MAC_PCU_TST_ADDAC__TEST_ARM__WIDTH 1 #define MAC_PCU_TST_ADDAC__TEST_ARM__MASK 0x00100000U #define MAC_PCU_TST_ADDAC__TEST_ARM__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_TST_ADDAC__TEST_ARM__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_TST_ADDAC__TEST_ARM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_TST_ADDAC__TEST_ARM__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_TST_ADDAC__TEST_ARM__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) #define MAC_PCU_TST_ADDAC__TYPE u_int32_t #define MAC_PCU_TST_ADDAC__READ 0x001fffffU #define MAC_PCU_TST_ADDAC__WRITE 0x001fffffU #endif /* __MAC_PCU_TST_ADDAC_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TST_ADDAC */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TST_ADDAC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_DEF_ANTENNA */ #ifndef __MAC_PCU_DEF_ANTENNA_MACRO__ #define __MAC_PCU_DEF_ANTENNA_MACRO__ /* macros for field VALUE */ #define MAC_PCU_DEF_ANTENNA__VALUE__SHIFT 0 #define MAC_PCU_DEF_ANTENNA__VALUE__WIDTH 24 #define MAC_PCU_DEF_ANTENNA__VALUE__MASK 0x00ffffffU #define MAC_PCU_DEF_ANTENNA__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU #define MAC_PCU_DEF_ANTENNA__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) #define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_PCU_DEF_ANTENNA__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) /* macros for field TX_DEF_ANT_SEL */ #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SHIFT 24 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MASK 0x01000000U #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field SLOW_TX_ANT_EN */ #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SHIFT 25 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MASK 0x02000000U #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) /* macros for field TX_CUR_ANT */ #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SHIFT 26 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MASK 0x04000000U #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__READ(src) \ (((u_int32_t)(src)\ & 0x04000000U) >> 26) #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WRITE(src) \ (((u_int32_t)(src)\ << 26) & 0x04000000U) #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x04000000U) | (((u_int32_t)(src) <<\ 26) & 0x04000000U) #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 26) & ~0x04000000U))) #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SET(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(1) << 26) #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__CLR(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(0) << 26) /* macros for field FAST_DEF_ANT */ #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SHIFT 27 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MASK 0x08000000U #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field RX_LNA_CONFIG_SEL */ #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SHIFT 28 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MASK 0x10000000U #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field FAST_TX_ANT_EN */ #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SHIFT 29 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MASK 0x20000000U #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field RX_ANT_EN */ #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SHIFT 30 #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MASK 0x40000000U #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) /* macros for field RX_ANT_DIV_ON */ #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SHIFT 31 #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WIDTH 1 #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MASK 0x80000000U #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define MAC_PCU_DEF_ANTENNA__TYPE u_int32_t #define MAC_PCU_DEF_ANTENNA__READ 0xffffffffU #define MAC_PCU_DEF_ANTENNA__WRITE 0xffffffffU #endif /* __MAC_PCU_DEF_ANTENNA_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_DEF_ANTENNA */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_DEF_ANTENNA__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_0 */ #ifndef __MAC_PCU_AES_MUTE_MASK_0_MACRO__ #define __MAC_PCU_AES_MUTE_MASK_0_MACRO__ /* macros for field FC */ #define MAC_PCU_AES_MUTE_MASK_0__FC__SHIFT 0 #define MAC_PCU_AES_MUTE_MASK_0__FC__WIDTH 16 #define MAC_PCU_AES_MUTE_MASK_0__FC__MASK 0x0000ffffU #define MAC_PCU_AES_MUTE_MASK_0__FC__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_AES_MUTE_MASK_0__FC__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_AES_MUTE_MASK_0__FC__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field QOS */ #define MAC_PCU_AES_MUTE_MASK_0__QOS__SHIFT 16 #define MAC_PCU_AES_MUTE_MASK_0__QOS__WIDTH 16 #define MAC_PCU_AES_MUTE_MASK_0__QOS__MASK 0xffff0000U #define MAC_PCU_AES_MUTE_MASK_0__QOS__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_PCU_AES_MUTE_MASK_0__QOS__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_PCU_AES_MUTE_MASK_0__QOS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_PCU_AES_MUTE_MASK_0__TYPE u_int32_t #define MAC_PCU_AES_MUTE_MASK_0__READ 0xffffffffU #define MAC_PCU_AES_MUTE_MASK_0__WRITE 0xffffffffU #endif /* __MAC_PCU_AES_MUTE_MASK_0_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_0 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_1 */ #ifndef __MAC_PCU_AES_MUTE_MASK_1_MACRO__ #define __MAC_PCU_AES_MUTE_MASK_1_MACRO__ /* macros for field SEQ */ #define MAC_PCU_AES_MUTE_MASK_1__SEQ__SHIFT 0 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__WIDTH 16 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__MASK 0x0000ffffU #define MAC_PCU_AES_MUTE_MASK_1__SEQ__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_AES_MUTE_MASK_1__SEQ__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_AES_MUTE_MASK_1__SEQ__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field FC_MGMT */ #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__SHIFT 16 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WIDTH 16 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MASK 0xffff0000U #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_PCU_AES_MUTE_MASK_1__TYPE u_int32_t #define MAC_PCU_AES_MUTE_MASK_1__READ 0xffffffffU #define MAC_PCU_AES_MUTE_MASK_1__WRITE 0xffffffffU #endif /* __MAC_PCU_AES_MUTE_MASK_1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_GATED_CLKS */ #ifndef __MAC_PCU_GATED_CLKS_MACRO__ #define __MAC_PCU_GATED_CLKS_MACRO__ /* macros for field GATED_TX */ #define MAC_PCU_GATED_CLKS__GATED_TX__SHIFT 1 #define MAC_PCU_GATED_CLKS__GATED_TX__WIDTH 1 #define MAC_PCU_GATED_CLKS__GATED_TX__MASK 0x00000002U #define MAC_PCU_GATED_CLKS__GATED_TX__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_GATED_CLKS__GATED_TX__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_GATED_CLKS__GATED_TX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_GATED_CLKS__GATED_TX__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_GATED_CLKS__GATED_TX__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field GATED_RX */ #define MAC_PCU_GATED_CLKS__GATED_RX__SHIFT 2 #define MAC_PCU_GATED_CLKS__GATED_RX__WIDTH 1 #define MAC_PCU_GATED_CLKS__GATED_RX__MASK 0x00000004U #define MAC_PCU_GATED_CLKS__GATED_RX__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_GATED_CLKS__GATED_RX__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_GATED_CLKS__GATED_RX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_GATED_CLKS__GATED_RX__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_GATED_CLKS__GATED_RX__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field GATED_REG */ #define MAC_PCU_GATED_CLKS__GATED_REG__SHIFT 3 #define MAC_PCU_GATED_CLKS__GATED_REG__WIDTH 1 #define MAC_PCU_GATED_CLKS__GATED_REG__MASK 0x00000008U #define MAC_PCU_GATED_CLKS__GATED_REG__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_GATED_CLKS__GATED_REG__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_GATED_CLKS__GATED_REG__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_GATED_CLKS__GATED_REG__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_GATED_CLKS__GATED_REG__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) #define MAC_PCU_GATED_CLKS__TYPE u_int32_t #define MAC_PCU_GATED_CLKS__READ 0x0000000eU #define MAC_PCU_GATED_CLKS__WRITE 0x0000000eU #endif /* __MAC_PCU_GATED_CLKS_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_GATED_CLKS */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_GATED_CLKS__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_2 */ #ifndef __MAC_PCU_OBS_BUS_2_MACRO__ #define __MAC_PCU_OBS_BUS_2_MACRO__ /* macros for field VALUE */ #define MAC_PCU_OBS_BUS_2__VALUE__SHIFT 0 #define MAC_PCU_OBS_BUS_2__VALUE__WIDTH 18 #define MAC_PCU_OBS_BUS_2__VALUE__MASK 0x0003ffffU #define MAC_PCU_OBS_BUS_2__VALUE__READ(src) (u_int32_t)(src) & 0x0003ffffU /* macros for field WCF_STATE */ #define MAC_PCU_OBS_BUS_2__WCF_STATE__SHIFT 18 #define MAC_PCU_OBS_BUS_2__WCF_STATE__WIDTH 4 #define MAC_PCU_OBS_BUS_2__WCF_STATE__MASK 0x003c0000U #define MAC_PCU_OBS_BUS_2__WCF_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x003c0000U) >> 18) /* macros for field WCF0_FULL */ #define MAC_PCU_OBS_BUS_2__WCF0_FULL__SHIFT 22 #define MAC_PCU_OBS_BUS_2__WCF0_FULL__WIDTH 1 #define MAC_PCU_OBS_BUS_2__WCF0_FULL__MASK 0x00400000U #define MAC_PCU_OBS_BUS_2__WCF0_FULL__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_PCU_OBS_BUS_2__WCF0_FULL__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_PCU_OBS_BUS_2__WCF0_FULL__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field WCF1_FULL */ #define MAC_PCU_OBS_BUS_2__WCF1_FULL__SHIFT 23 #define MAC_PCU_OBS_BUS_2__WCF1_FULL__WIDTH 1 #define MAC_PCU_OBS_BUS_2__WCF1_FULL__MASK 0x00800000U #define MAC_PCU_OBS_BUS_2__WCF1_FULL__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_PCU_OBS_BUS_2__WCF1_FULL__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_PCU_OBS_BUS_2__WCF1_FULL__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field WCF_COUNT */ #define MAC_PCU_OBS_BUS_2__WCF_COUNT__SHIFT 24 #define MAC_PCU_OBS_BUS_2__WCF_COUNT__WIDTH 5 #define MAC_PCU_OBS_BUS_2__WCF_COUNT__MASK 0x1f000000U #define MAC_PCU_OBS_BUS_2__WCF_COUNT__READ(src) \ (((u_int32_t)(src)\ & 0x1f000000U) >> 24) /* macros for field MACBB_ALL_AWAKE */ #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SHIFT 29 #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__WIDTH 1 #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__MASK 0x20000000U #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) #define MAC_PCU_OBS_BUS_2__TYPE u_int32_t #define MAC_PCU_OBS_BUS_2__READ 0x3fffffffU #endif /* __MAC_PCU_OBS_BUS_2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_1 */ #ifndef __MAC_PCU_OBS_BUS_1_MACRO__ #define __MAC_PCU_OBS_BUS_1_MACRO__ /* macros for field PCU_DIRECTED */ #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SHIFT 0 #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__WIDTH 1 #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__MASK 0x00000001U #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field PCU_RX_END */ #define MAC_PCU_OBS_BUS_1__PCU_RX_END__SHIFT 1 #define MAC_PCU_OBS_BUS_1__PCU_RX_END__WIDTH 1 #define MAC_PCU_OBS_BUS_1__PCU_RX_END__MASK 0x00000002U #define MAC_PCU_OBS_BUS_1__PCU_RX_END__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_OBS_BUS_1__PCU_RX_END__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_OBS_BUS_1__PCU_RX_END__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field RX_WEP */ #define MAC_PCU_OBS_BUS_1__RX_WEP__SHIFT 2 #define MAC_PCU_OBS_BUS_1__RX_WEP__WIDTH 1 #define MAC_PCU_OBS_BUS_1__RX_WEP__MASK 0x00000004U #define MAC_PCU_OBS_BUS_1__RX_WEP__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_OBS_BUS_1__RX_WEP__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_OBS_BUS_1__RX_WEP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field RX_MY_BEACON */ #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SHIFT 3 #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__WIDTH 1 #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__MASK 0x00000008U #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field FILTER_PASS */ #define MAC_PCU_OBS_BUS_1__FILTER_PASS__SHIFT 4 #define MAC_PCU_OBS_BUS_1__FILTER_PASS__WIDTH 1 #define MAC_PCU_OBS_BUS_1__FILTER_PASS__MASK 0x00000010U #define MAC_PCU_OBS_BUS_1__FILTER_PASS__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_OBS_BUS_1__FILTER_PASS__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_OBS_BUS_1__FILTER_PASS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field TX_HCF */ #define MAC_PCU_OBS_BUS_1__TX_HCF__SHIFT 5 #define MAC_PCU_OBS_BUS_1__TX_HCF__WIDTH 1 #define MAC_PCU_OBS_BUS_1__TX_HCF__MASK 0x00000020U #define MAC_PCU_OBS_BUS_1__TX_HCF__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_OBS_BUS_1__TX_HCF__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_OBS_BUS_1__TX_HCF__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field TM_QUIET_TIME */ #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SHIFT 6 #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__WIDTH 1 #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__MASK 0x00000040U #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field PCU_CHANNEL_IDLE */ #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SHIFT 7 #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__WIDTH 1 #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__MASK 0x00000080U #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field TX_HOLD */ #define MAC_PCU_OBS_BUS_1__TX_HOLD__SHIFT 8 #define MAC_PCU_OBS_BUS_1__TX_HOLD__WIDTH 1 #define MAC_PCU_OBS_BUS_1__TX_HOLD__MASK 0x00000100U #define MAC_PCU_OBS_BUS_1__TX_HOLD__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_OBS_BUS_1__TX_HOLD__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_OBS_BUS_1__TX_HOLD__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field TX_FRAME */ #define MAC_PCU_OBS_BUS_1__TX_FRAME__SHIFT 9 #define MAC_PCU_OBS_BUS_1__TX_FRAME__WIDTH 1 #define MAC_PCU_OBS_BUS_1__TX_FRAME__MASK 0x00000200U #define MAC_PCU_OBS_BUS_1__TX_FRAME__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_PCU_OBS_BUS_1__TX_FRAME__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_PCU_OBS_BUS_1__TX_FRAME__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field RX_FRAME */ #define MAC_PCU_OBS_BUS_1__RX_FRAME__SHIFT 10 #define MAC_PCU_OBS_BUS_1__RX_FRAME__WIDTH 1 #define MAC_PCU_OBS_BUS_1__RX_FRAME__MASK 0x00000400U #define MAC_PCU_OBS_BUS_1__RX_FRAME__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_PCU_OBS_BUS_1__RX_FRAME__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_PCU_OBS_BUS_1__RX_FRAME__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field RX_CLEAR */ #define MAC_PCU_OBS_BUS_1__RX_CLEAR__SHIFT 11 #define MAC_PCU_OBS_BUS_1__RX_CLEAR__WIDTH 1 #define MAC_PCU_OBS_BUS_1__RX_CLEAR__MASK 0x00000800U #define MAC_PCU_OBS_BUS_1__RX_CLEAR__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_OBS_BUS_1__RX_CLEAR__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_OBS_BUS_1__RX_CLEAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field WEP_STATE */ #define MAC_PCU_OBS_BUS_1__WEP_STATE__SHIFT 12 #define MAC_PCU_OBS_BUS_1__WEP_STATE__WIDTH 6 #define MAC_PCU_OBS_BUS_1__WEP_STATE__MASK 0x0003f000U #define MAC_PCU_OBS_BUS_1__WEP_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x0003f000U) >> 12) /* macros for field RX_STATE */ #define MAC_PCU_OBS_BUS_1__RX_STATE__SHIFT 20 #define MAC_PCU_OBS_BUS_1__RX_STATE__WIDTH 5 #define MAC_PCU_OBS_BUS_1__RX_STATE__MASK 0x01f00000U #define MAC_PCU_OBS_BUS_1__RX_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x01f00000U) >> 20) /* macros for field TX_STATE */ #define MAC_PCU_OBS_BUS_1__TX_STATE__SHIFT 25 #define MAC_PCU_OBS_BUS_1__TX_STATE__WIDTH 6 #define MAC_PCU_OBS_BUS_1__TX_STATE__MASK 0x7e000000U #define MAC_PCU_OBS_BUS_1__TX_STATE__READ(src) \ (((u_int32_t)(src)\ & 0x7e000000U) >> 25) #define MAC_PCU_OBS_BUS_1__TYPE u_int32_t #define MAC_PCU_OBS_BUS_1__READ 0x7ff3ffffU #endif /* __MAC_PCU_OBS_BUS_1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_DYM_MIMO_PWR_SAVE */ #ifndef __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ #define __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ /* macros for field USE_MAC_CTRL */ #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SHIFT 0 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WIDTH 1 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MASK 0x00000001U #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field HW_CTRL_EN */ #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SHIFT 1 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WIDTH 1 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MASK 0x00000002U #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field SW_CHAIN_MASK_SEL */ #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SHIFT 2 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WIDTH 1 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MASK 0x00000004U #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field LOW_PWR_CHAIN_MASK */ #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__SHIFT 4 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WIDTH 3 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MASK 0x00000070U #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__READ(src) \ (((u_int32_t)(src)\ & 0x00000070U) >> 4) #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000070U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000070U) | (((u_int32_t)(src) <<\ 4) & 0x00000070U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000070U))) /* macros for field HI_PWR_CHAIN_MASK */ #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__SHIFT 8 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WIDTH 3 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MASK 0x00000700U #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__READ(src) \ (((u_int32_t)(src)\ & 0x00000700U) >> 8) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000700U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000700U) | (((u_int32_t)(src) <<\ 8) & 0x00000700U) #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000700U))) #define MAC_PCU_DYM_MIMO_PWR_SAVE__TYPE u_int32_t #define MAC_PCU_DYM_MIMO_PWR_SAVE__READ 0x00000777U #define MAC_PCU_DYM_MIMO_PWR_SAVE__WRITE 0x00000777U #endif /* __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_DYM_MIMO_PWR_SAVE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_DYM_MIMO_PWR_SAVE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */ #ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ #define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__SHIFT 0 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WIDTH 32 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MASK 0xffffffffU #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__TYPE u_int32_t #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__READ 0xffffffffU #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__WRITE 0xffffffffU #endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__NUM \ 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */ #ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ #define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__SHIFT 0 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WIDTH 32 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MASK 0xffffffffU #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__TYPE u_int32_t #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__READ 0xffffffffU #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__WRITE 0xffffffffU #endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__NUM \ 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_LAST_BEACON_TSF */ #ifndef __MAC_PCU_LAST_BEACON_TSF_MACRO__ #define __MAC_PCU_LAST_BEACON_TSF_MACRO__ /* macros for field VALUE */ #define MAC_PCU_LAST_BEACON_TSF__VALUE__SHIFT 0 #define MAC_PCU_LAST_BEACON_TSF__VALUE__WIDTH 32 #define MAC_PCU_LAST_BEACON_TSF__VALUE__MASK 0xffffffffU #define MAC_PCU_LAST_BEACON_TSF__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_LAST_BEACON_TSF__TYPE u_int32_t #define MAC_PCU_LAST_BEACON_TSF__READ 0xffffffffU #endif /* __MAC_PCU_LAST_BEACON_TSF_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_LAST_BEACON_TSF */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_LAST_BEACON_TSF__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_NAV */ #ifndef __MAC_PCU_NAV_MACRO__ #define __MAC_PCU_NAV_MACRO__ /* macros for field VALUE */ #define MAC_PCU_NAV__VALUE__SHIFT 0 #define MAC_PCU_NAV__VALUE__WIDTH 26 #define MAC_PCU_NAV__VALUE__MASK 0x03ffffffU #define MAC_PCU_NAV__VALUE__READ(src) (u_int32_t)(src) & 0x03ffffffU #define MAC_PCU_NAV__VALUE__WRITE(src) ((u_int32_t)(src) & 0x03ffffffU) #define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x03ffffffU) | ((u_int32_t)(src) &\ 0x03ffffffU) #define MAC_PCU_NAV__VALUE__VERIFY(src) (!(((u_int32_t)(src) & ~0x03ffffffU))) #define MAC_PCU_NAV__TYPE u_int32_t #define MAC_PCU_NAV__READ 0x03ffffffU #define MAC_PCU_NAV__WRITE 0x03ffffffU #endif /* __MAC_PCU_NAV_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_NAV */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_NAV__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_SUCCESS_CNT */ #ifndef __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ #define __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_RTS_SUCCESS_CNT__VALUE__SHIFT 0 #define MAC_PCU_RTS_SUCCESS_CNT__VALUE__WIDTH 16 #define MAC_PCU_RTS_SUCCESS_CNT__VALUE__MASK 0x0000ffffU #define MAC_PCU_RTS_SUCCESS_CNT__VALUE__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_PCU_RTS_SUCCESS_CNT__TYPE u_int32_t #define MAC_PCU_RTS_SUCCESS_CNT__READ 0x0000ffffU #endif /* __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RTS_SUCCESS_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_SUCCESS_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_FAIL_CNT */ #ifndef __MAC_PCU_RTS_FAIL_CNT_MACRO__ #define __MAC_PCU_RTS_FAIL_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_RTS_FAIL_CNT__VALUE__SHIFT 0 #define MAC_PCU_RTS_FAIL_CNT__VALUE__WIDTH 16 #define MAC_PCU_RTS_FAIL_CNT__VALUE__MASK 0x0000ffffU #define MAC_PCU_RTS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_RTS_FAIL_CNT__TYPE u_int32_t #define MAC_PCU_RTS_FAIL_CNT__READ 0x0000ffffU #endif /* __MAC_PCU_RTS_FAIL_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RTS_FAIL_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_FAIL_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_FAIL_CNT */ #ifndef __MAC_PCU_ACK_FAIL_CNT_MACRO__ #define __MAC_PCU_ACK_FAIL_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_ACK_FAIL_CNT__VALUE__SHIFT 0 #define MAC_PCU_ACK_FAIL_CNT__VALUE__WIDTH 16 #define MAC_PCU_ACK_FAIL_CNT__VALUE__MASK 0x0000ffffU #define MAC_PCU_ACK_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_ACK_FAIL_CNT__TYPE u_int32_t #define MAC_PCU_ACK_FAIL_CNT__READ 0x0000ffffU #endif /* __MAC_PCU_ACK_FAIL_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_ACK_FAIL_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_FAIL_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_FCS_FAIL_CNT */ #ifndef __MAC_PCU_FCS_FAIL_CNT_MACRO__ #define __MAC_PCU_FCS_FAIL_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_FCS_FAIL_CNT__VALUE__SHIFT 0 #define MAC_PCU_FCS_FAIL_CNT__VALUE__WIDTH 16 #define MAC_PCU_FCS_FAIL_CNT__VALUE__MASK 0x0000ffffU #define MAC_PCU_FCS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_FCS_FAIL_CNT__TYPE u_int32_t #define MAC_PCU_FCS_FAIL_CNT__READ 0x0000ffffU #endif /* __MAC_PCU_FCS_FAIL_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_FCS_FAIL_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_FCS_FAIL_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BEACON_CNT */ #ifndef __MAC_PCU_BEACON_CNT_MACRO__ #define __MAC_PCU_BEACON_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BEACON_CNT__VALUE__SHIFT 0 #define MAC_PCU_BEACON_CNT__VALUE__WIDTH 16 #define MAC_PCU_BEACON_CNT__VALUE__MASK 0x0000ffffU #define MAC_PCU_BEACON_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_BEACON_CNT__TYPE u_int32_t #define MAC_PCU_BEACON_CNT__READ 0x0000ffffU #endif /* __MAC_PCU_BEACON_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BEACON_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BEACON_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_SLOT_ALERT_CNTL */ #ifndef __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ #define __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__SHIFT 0 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WIDTH 16 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MASK 0x0000ffffU #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__TYPE u_int32_t #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__READ 0x0000ffffU #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__WRITE 0x0000ffffU #endif /* __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TDMA_SLOT_ALERT_CNTL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_SLOT_ALERT_CNTL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BASIC_SET */ #ifndef __MAC_PCU_BASIC_SET_MACRO__ #define __MAC_PCU_BASIC_SET_MACRO__ /* macros for field MCS */ #define MAC_PCU_BASIC_SET__MCS__SHIFT 0 #define MAC_PCU_BASIC_SET__MCS__WIDTH 32 #define MAC_PCU_BASIC_SET__MCS__MASK 0xffffffffU #define MAC_PCU_BASIC_SET__MCS__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_BASIC_SET__MCS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BASIC_SET__MCS__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BASIC_SET__TYPE u_int32_t #define MAC_PCU_BASIC_SET__READ 0xffffffffU #define MAC_PCU_BASIC_SET__WRITE 0xffffffffU #endif /* __MAC_PCU_BASIC_SET_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BASIC_SET */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BASIC_SET__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MGMT_SEQ */ #ifndef __MAC_PCU_MGMT_SEQ_MACRO__ #define __MAC_PCU_MGMT_SEQ_MACRO__ /* macros for field MIN */ #define MAC_PCU_MGMT_SEQ__MIN__SHIFT 0 #define MAC_PCU_MGMT_SEQ__MIN__WIDTH 12 #define MAC_PCU_MGMT_SEQ__MIN__MASK 0x00000fffU #define MAC_PCU_MGMT_SEQ__MIN__READ(src) (u_int32_t)(src) & 0x00000fffU #define MAC_PCU_MGMT_SEQ__MIN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) #define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000fffU) | ((u_int32_t)(src) &\ 0x00000fffU) #define MAC_PCU_MGMT_SEQ__MIN__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000fffU))) /* macros for field MAX */ #define MAC_PCU_MGMT_SEQ__MAX__SHIFT 16 #define MAC_PCU_MGMT_SEQ__MAX__WIDTH 12 #define MAC_PCU_MGMT_SEQ__MAX__MASK 0x0fff0000U #define MAC_PCU_MGMT_SEQ__MAX__READ(src) \ (((u_int32_t)(src)\ & 0x0fff0000U) >> 16) #define MAC_PCU_MGMT_SEQ__MAX__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x0fff0000U) #define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0fff0000U) | (((u_int32_t)(src) <<\ 16) & 0x0fff0000U) #define MAC_PCU_MGMT_SEQ__MAX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x0fff0000U))) #define MAC_PCU_MGMT_SEQ__TYPE u_int32_t #define MAC_PCU_MGMT_SEQ__READ 0x0fff0fffU #define MAC_PCU_MGMT_SEQ__WRITE 0x0fff0fffU #endif /* __MAC_PCU_MGMT_SEQ_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MGMT_SEQ */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MGMT_SEQ__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT1 */ #ifndef __MAC_PCU_BF_RPT1_MACRO__ #define __MAC_PCU_BF_RPT1_MACRO__ /* macros for field V_ACTION_VALUE */ #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__SHIFT 0 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WIDTH 8 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MASK 0x000000ffU #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field CV_ACTION_VALUE */ #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__SHIFT 8 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WIDTH 8 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MASK 0x0000ff00U #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field CATEGORY_VALUE */ #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__SHIFT 16 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WIDTH 8 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MASK 0x00ff0000U #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field FRAME_SUBTYPE_VALUE */ #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__SHIFT 24 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WIDTH 4 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MASK 0x0f000000U #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0x0f000000U) >> 24) #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x0f000000U) #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0f000000U) | (((u_int32_t)(src) <<\ 24) & 0x0f000000U) #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x0f000000U))) /* macros for field FRAME_TYPE_VALUE */ #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__SHIFT 28 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WIDTH 2 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MASK 0x30000000U #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0x30000000U) >> 28) #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x30000000U) #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x30000000U) | (((u_int32_t)(src) <<\ 28) & 0x30000000U) #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x30000000U))) #define MAC_PCU_BF_RPT1__TYPE u_int32_t #define MAC_PCU_BF_RPT1__READ 0x3fffffffU #define MAC_PCU_BF_RPT1__WRITE 0x3fffffffU #endif /* __MAC_PCU_BF_RPT1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT2 */ #ifndef __MAC_PCU_BF_RPT2_MACRO__ #define __MAC_PCU_BF_RPT2_MACRO__ /* macros for field FRAME_SUBTYPE_VALUE */ #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__SHIFT 0 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WIDTH 4 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MASK 0x0000000fU #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__READ(src) \ (u_int32_t)(src)\ & 0x0000000fU #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000000fU) #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000000fU))) #define MAC_PCU_BF_RPT2__TYPE u_int32_t #define MAC_PCU_BF_RPT2__READ 0x0000000fU #define MAC_PCU_BF_RPT2__WRITE 0x0000000fU #endif /* __MAC_PCU_BF_RPT2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_1 */ #ifndef __MAC_PCU_TX_ANT_1_MACRO__ #define __MAC_PCU_TX_ANT_1_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TX_ANT_1__VALUE__SHIFT 0 #define MAC_PCU_TX_ANT_1__VALUE__WIDTH 32 #define MAC_PCU_TX_ANT_1__VALUE__MASK 0xffffffffU #define MAC_PCU_TX_ANT_1__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TX_ANT_1__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TX_ANT_1__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TX_ANT_1__TYPE u_int32_t #define MAC_PCU_TX_ANT_1__READ 0xffffffffU #define MAC_PCU_TX_ANT_1__WRITE 0xffffffffU #endif /* __MAC_PCU_TX_ANT_1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_2 */ #ifndef __MAC_PCU_TX_ANT_2_MACRO__ #define __MAC_PCU_TX_ANT_2_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TX_ANT_2__VALUE__SHIFT 0 #define MAC_PCU_TX_ANT_2__VALUE__WIDTH 32 #define MAC_PCU_TX_ANT_2__VALUE__MASK 0xffffffffU #define MAC_PCU_TX_ANT_2__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TX_ANT_2__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TX_ANT_2__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TX_ANT_2__TYPE u_int32_t #define MAC_PCU_TX_ANT_2__READ 0xffffffffU #define MAC_PCU_TX_ANT_2__WRITE 0xffffffffU #endif /* __MAC_PCU_TX_ANT_2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_3 */ #ifndef __MAC_PCU_TX_ANT_3_MACRO__ #define __MAC_PCU_TX_ANT_3_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TX_ANT_3__VALUE__SHIFT 0 #define MAC_PCU_TX_ANT_3__VALUE__WIDTH 32 #define MAC_PCU_TX_ANT_3__VALUE__MASK 0xffffffffU #define MAC_PCU_TX_ANT_3__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TX_ANT_3__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TX_ANT_3__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TX_ANT_3__TYPE u_int32_t #define MAC_PCU_TX_ANT_3__READ 0xffffffffU #define MAC_PCU_TX_ANT_3__WRITE 0xffffffffU #endif /* __MAC_PCU_TX_ANT_3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_4 */ #ifndef __MAC_PCU_TX_ANT_4_MACRO__ #define __MAC_PCU_TX_ANT_4_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TX_ANT_4__VALUE__SHIFT 0 #define MAC_PCU_TX_ANT_4__VALUE__WIDTH 32 #define MAC_PCU_TX_ANT_4__VALUE__MASK 0xffffffffU #define MAC_PCU_TX_ANT_4__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TX_ANT_4__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TX_ANT_4__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TX_ANT_4__TYPE u_int32_t #define MAC_PCU_TX_ANT_4__READ 0xffffffffU #define MAC_PCU_TX_ANT_4__WRITE 0xffffffffU #endif /* __MAC_PCU_TX_ANT_4_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_4 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_4__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_XRMODE */ #ifndef __MAC_PCU_XRMODE_MACRO__ #define __MAC_PCU_XRMODE_MACRO__ /* macros for field POLL_TYPE */ #define MAC_PCU_XRMODE__POLL_TYPE__SHIFT 0 #define MAC_PCU_XRMODE__POLL_TYPE__WIDTH 6 #define MAC_PCU_XRMODE__POLL_TYPE__MASK 0x0000003fU #define MAC_PCU_XRMODE__POLL_TYPE__READ(src) (u_int32_t)(src) & 0x0000003fU #define MAC_PCU_XRMODE__POLL_TYPE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) #define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000003fU) | ((u_int32_t)(src) &\ 0x0000003fU) #define MAC_PCU_XRMODE__POLL_TYPE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000003fU))) /* macros for field WAIT_FOR_POLL */ #define MAC_PCU_XRMODE__WAIT_FOR_POLL__SHIFT 7 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__WIDTH 1 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__MASK 0x00000080U #define MAC_PCU_XRMODE__WAIT_FOR_POLL__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_XRMODE__WAIT_FOR_POLL__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_XRMODE__WAIT_FOR_POLL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_XRMODE__WAIT_FOR_POLL__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_XRMODE__WAIT_FOR_POLL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field FRAME_HOLD */ #define MAC_PCU_XRMODE__FRAME_HOLD__SHIFT 20 #define MAC_PCU_XRMODE__FRAME_HOLD__WIDTH 12 #define MAC_PCU_XRMODE__FRAME_HOLD__MASK 0xfff00000U #define MAC_PCU_XRMODE__FRAME_HOLD__READ(src) \ (((u_int32_t)(src)\ & 0xfff00000U) >> 20) #define MAC_PCU_XRMODE__FRAME_HOLD__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0xfff00000U) #define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xfff00000U) | (((u_int32_t)(src) <<\ 20) & 0xfff00000U) #define MAC_PCU_XRMODE__FRAME_HOLD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0xfff00000U))) #define MAC_PCU_XRMODE__TYPE u_int32_t #define MAC_PCU_XRMODE__READ 0xfff000bfU #define MAC_PCU_XRMODE__WRITE 0xfff000bfU #endif /* __MAC_PCU_XRMODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_XRMODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_XRMODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_XRDEL */ #ifndef __MAC_PCU_XRDEL_MACRO__ #define __MAC_PCU_XRDEL_MACRO__ /* macros for field SLOT_DELAY */ #define MAC_PCU_XRDEL__SLOT_DELAY__SHIFT 0 #define MAC_PCU_XRDEL__SLOT_DELAY__WIDTH 16 #define MAC_PCU_XRDEL__SLOT_DELAY__MASK 0x0000ffffU #define MAC_PCU_XRDEL__SLOT_DELAY__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_XRDEL__SLOT_DELAY__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_XRDEL__SLOT_DELAY__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field CHIRP_DATA_DELAY */ #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__SHIFT 16 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WIDTH 16 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MASK 0xffff0000U #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_PCU_XRDEL__TYPE u_int32_t #define MAC_PCU_XRDEL__READ 0xffffffffU #define MAC_PCU_XRDEL__WRITE 0xffffffffU #endif /* __MAC_PCU_XRDEL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_XRDEL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_XRDEL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_XRTO */ #ifndef __MAC_PCU_XRTO_MACRO__ #define __MAC_PCU_XRTO_MACRO__ /* macros for field CHIRP_TIMEOUT */ #define MAC_PCU_XRTO__CHIRP_TIMEOUT__SHIFT 0 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__WIDTH 16 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__MASK 0x0000ffffU #define MAC_PCU_XRTO__CHIRP_TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_XRTO__CHIRP_TIMEOUT__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_XRTO__CHIRP_TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field POLL_TIMEOUT */ #define MAC_PCU_XRTO__POLL_TIMEOUT__SHIFT 16 #define MAC_PCU_XRTO__POLL_TIMEOUT__WIDTH 16 #define MAC_PCU_XRTO__POLL_TIMEOUT__MASK 0xffff0000U #define MAC_PCU_XRTO__POLL_TIMEOUT__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_PCU_XRTO__POLL_TIMEOUT__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_PCU_XRTO__POLL_TIMEOUT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_PCU_XRTO__TYPE u_int32_t #define MAC_PCU_XRTO__READ 0xffffffffU #define MAC_PCU_XRTO__WRITE 0xffffffffU #endif /* __MAC_PCU_XRTO_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_XRTO */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_XRTO__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_XRCRP */ #ifndef __MAC_PCU_XRCRP_MACRO__ #define __MAC_PCU_XRCRP_MACRO__ /* macros for field SEND_CHIRP */ #define MAC_PCU_XRCRP__SEND_CHIRP__SHIFT 0 #define MAC_PCU_XRCRP__SEND_CHIRP__WIDTH 1 #define MAC_PCU_XRCRP__SEND_CHIRP__MASK 0x00000001U #define MAC_PCU_XRCRP__SEND_CHIRP__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_XRCRP__SEND_CHIRP__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_XRCRP__SEND_CHIRP__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_XRCRP__SEND_CHIRP__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_XRCRP__SEND_CHIRP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field CHIRP_GAP */ #define MAC_PCU_XRCRP__CHIRP_GAP__SHIFT 16 #define MAC_PCU_XRCRP__CHIRP_GAP__WIDTH 16 #define MAC_PCU_XRCRP__CHIRP_GAP__MASK 0xffff0000U #define MAC_PCU_XRCRP__CHIRP_GAP__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_PCU_XRCRP__CHIRP_GAP__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_PCU_XRCRP__CHIRP_GAP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_PCU_XRCRP__TYPE u_int32_t #define MAC_PCU_XRCRP__READ 0xffff0001U #define MAC_PCU_XRCRP__WRITE 0xffff0001U #endif /* __MAC_PCU_XRCRP_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_XRCRP */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_XRCRP__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_XRSTMP */ #ifndef __MAC_PCU_XRSTMP_MACRO__ #define __MAC_PCU_XRSTMP_MACRO__ /* macros for field RX_ABORT_RSSI */ #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SHIFT 0 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WIDTH 1 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MASK 0x00000001U #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field RX_ABORT_BSSID */ #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SHIFT 1 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WIDTH 1 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MASK 0x00000002U #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field TX_STOMP_RSSI */ #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SHIFT 2 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WIDTH 1 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MASK 0x00000004U #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field TX_STOMP_BSSID */ #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SHIFT 3 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WIDTH 1 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MASK 0x00000008U #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field TX_STOMP_DATA */ #define MAC_PCU_XRSTMP__TX_STOMP_DATA__SHIFT 4 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__WIDTH 1 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__MASK 0x00000010U #define MAC_PCU_XRSTMP__TX_STOMP_DATA__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_XRSTMP__TX_STOMP_DATA__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_XRSTMP__TX_STOMP_DATA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_XRSTMP__TX_STOMP_DATA__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_XRSTMP__TX_STOMP_DATA__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field RX_ABORT_DATA */ #define MAC_PCU_XRSTMP__RX_ABORT_DATA__SHIFT 5 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__WIDTH 1 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__MASK 0x00000020U #define MAC_PCU_XRSTMP__RX_ABORT_DATA__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_XRSTMP__RX_ABORT_DATA__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_XRSTMP__RX_ABORT_DATA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_XRSTMP__RX_ABORT_DATA__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_XRSTMP__RX_ABORT_DATA__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field TX_STOMP_RSSI_THRESH */ #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__SHIFT 8 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WIDTH 8 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MASK 0x0000ff00U #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field RX_ABORT_RSSI_THRESH */ #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__SHIFT 16 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WIDTH 8 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MASK 0x00ff0000U #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) #define MAC_PCU_XRSTMP__TYPE u_int32_t #define MAC_PCU_XRSTMP__READ 0x00ffff3fU #define MAC_PCU_XRSTMP__WRITE 0x00ffff3fU #endif /* __MAC_PCU_XRSTMP_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_XRSTMP */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_XRSTMP__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP1 */ #ifndef __MAC_PCU_SLP1_MACRO__ #define __MAC_PCU_SLP1_MACRO__ /* macros for field ASSUME_DTIM */ #define MAC_PCU_SLP1__ASSUME_DTIM__SHIFT 19 #define MAC_PCU_SLP1__ASSUME_DTIM__WIDTH 1 #define MAC_PCU_SLP1__ASSUME_DTIM__MASK 0x00080000U #define MAC_PCU_SLP1__ASSUME_DTIM__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_SLP1__ASSUME_DTIM__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_PCU_SLP1__ASSUME_DTIM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_PCU_SLP1__ASSUME_DTIM__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_SLP1__ASSUME_DTIM__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field CAB_TIMEOUT */ #define MAC_PCU_SLP1__CAB_TIMEOUT__SHIFT 21 #define MAC_PCU_SLP1__CAB_TIMEOUT__WIDTH 11 #define MAC_PCU_SLP1__CAB_TIMEOUT__MASK 0xffe00000U #define MAC_PCU_SLP1__CAB_TIMEOUT__READ(src) \ (((u_int32_t)(src)\ & 0xffe00000U) >> 21) #define MAC_PCU_SLP1__CAB_TIMEOUT__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0xffe00000U) #define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffe00000U) | (((u_int32_t)(src) <<\ 21) & 0xffe00000U) #define MAC_PCU_SLP1__CAB_TIMEOUT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0xffe00000U))) #define MAC_PCU_SLP1__TYPE u_int32_t #define MAC_PCU_SLP1__READ 0xffe80000U #define MAC_PCU_SLP1__WRITE 0xffe80000U #endif /* __MAC_PCU_SLP1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP2 */ #ifndef __MAC_PCU_SLP2_MACRO__ #define __MAC_PCU_SLP2_MACRO__ /* macros for field BEACON_TIMEOUT */ #define MAC_PCU_SLP2__BEACON_TIMEOUT__SHIFT 21 #define MAC_PCU_SLP2__BEACON_TIMEOUT__WIDTH 11 #define MAC_PCU_SLP2__BEACON_TIMEOUT__MASK 0xffe00000U #define MAC_PCU_SLP2__BEACON_TIMEOUT__READ(src) \ (((u_int32_t)(src)\ & 0xffe00000U) >> 21) #define MAC_PCU_SLP2__BEACON_TIMEOUT__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0xffe00000U) #define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffe00000U) | (((u_int32_t)(src) <<\ 21) & 0xffe00000U) #define MAC_PCU_SLP2__BEACON_TIMEOUT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0xffe00000U))) #define MAC_PCU_SLP2__TYPE u_int32_t #define MAC_PCU_SLP2__READ 0xffe00000U #define MAC_PCU_SLP2__WRITE 0xffe00000U #endif /* __MAC_PCU_SLP2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_DEFAULT */ #ifndef __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ #define __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ /* macros for field MMSS */ #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__SHIFT 0 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WIDTH 3 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MASK 0x00000007U #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__READ(src) \ (u_int32_t)(src)\ & 0x00000007U #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000007U) #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000007U) | ((u_int32_t)(src) &\ 0x00000007U) #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000007U))) /* macros for field CEC */ #define MAC_PCU_SELF_GEN_DEFAULT__CEC__SHIFT 3 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__WIDTH 2 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__MASK 0x00000018U #define MAC_PCU_SELF_GEN_DEFAULT__CEC__READ(src) \ (((u_int32_t)(src)\ & 0x00000018U) >> 3) #define MAC_PCU_SELF_GEN_DEFAULT__CEC__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000018U) #define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000018U) | (((u_int32_t)(src) <<\ 3) & 0x00000018U) #define MAC_PCU_SELF_GEN_DEFAULT__CEC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000018U))) /* macros for field STAGGER_SOUNDING */ #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SHIFT 5 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WIDTH 1 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MASK 0x00000020U #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) #define MAC_PCU_SELF_GEN_DEFAULT__TYPE u_int32_t #define MAC_PCU_SELF_GEN_DEFAULT__READ 0x0000003fU #define MAC_PCU_SELF_GEN_DEFAULT__WRITE 0x0000003fU #endif /* __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_DEFAULT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_DEFAULT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_L32 */ #ifndef __MAC_PCU_ADDR1_MASK_L32_MACRO__ #define __MAC_PCU_ADDR1_MASK_L32_MACRO__ /* macros for field VALUE */ #define MAC_PCU_ADDR1_MASK_L32__VALUE__SHIFT 0 #define MAC_PCU_ADDR1_MASK_L32__VALUE__WIDTH 32 #define MAC_PCU_ADDR1_MASK_L32__VALUE__MASK 0xffffffffU #define MAC_PCU_ADDR1_MASK_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_ADDR1_MASK_L32__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_ADDR1_MASK_L32__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_ADDR1_MASK_L32__TYPE u_int32_t #define MAC_PCU_ADDR1_MASK_L32__READ 0xffffffffU #define MAC_PCU_ADDR1_MASK_L32__WRITE 0xffffffffU #endif /* __MAC_PCU_ADDR1_MASK_L32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_L32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_L32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_U16 */ #ifndef __MAC_PCU_ADDR1_MASK_U16_MACRO__ #define __MAC_PCU_ADDR1_MASK_U16_MACRO__ /* macros for field VALUE */ #define MAC_PCU_ADDR1_MASK_U16__VALUE__SHIFT 0 #define MAC_PCU_ADDR1_MASK_U16__VALUE__WIDTH 16 #define MAC_PCU_ADDR1_MASK_U16__VALUE__MASK 0x0000ffffU #define MAC_PCU_ADDR1_MASK_U16__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_ADDR1_MASK_U16__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_ADDR1_MASK_U16__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_PCU_ADDR1_MASK_U16__TYPE u_int32_t #define MAC_PCU_ADDR1_MASK_U16__READ 0x0000ffffU #define MAC_PCU_ADDR1_MASK_U16__WRITE 0x0000ffffU #endif /* __MAC_PCU_ADDR1_MASK_U16_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_U16 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_U16__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TPC */ #ifndef __MAC_PCU_TPC_MACRO__ #define __MAC_PCU_TPC_MACRO__ /* macros for field ACK_PWR */ #define MAC_PCU_TPC__ACK_PWR__SHIFT 0 #define MAC_PCU_TPC__ACK_PWR__WIDTH 6 #define MAC_PCU_TPC__ACK_PWR__MASK 0x0000003fU #define MAC_PCU_TPC__ACK_PWR__READ(src) (u_int32_t)(src) & 0x0000003fU #define MAC_PCU_TPC__ACK_PWR__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) #define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000003fU) | ((u_int32_t)(src) &\ 0x0000003fU) #define MAC_PCU_TPC__ACK_PWR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000003fU))) /* macros for field CTS_PWR */ #define MAC_PCU_TPC__CTS_PWR__SHIFT 8 #define MAC_PCU_TPC__CTS_PWR__WIDTH 6 #define MAC_PCU_TPC__CTS_PWR__MASK 0x00003f00U #define MAC_PCU_TPC__CTS_PWR__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8) #define MAC_PCU_TPC__CTS_PWR__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00003f00U) #define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00003f00U) | (((u_int32_t)(src) <<\ 8) & 0x00003f00U) #define MAC_PCU_TPC__CTS_PWR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00003f00U))) /* macros for field CHIRP_PWR */ #define MAC_PCU_TPC__CHIRP_PWR__SHIFT 16 #define MAC_PCU_TPC__CHIRP_PWR__WIDTH 6 #define MAC_PCU_TPC__CHIRP_PWR__MASK 0x003f0000U #define MAC_PCU_TPC__CHIRP_PWR__READ(src) \ (((u_int32_t)(src)\ & 0x003f0000U) >> 16) #define MAC_PCU_TPC__CHIRP_PWR__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x003f0000U) #define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x003f0000U) | (((u_int32_t)(src) <<\ 16) & 0x003f0000U) #define MAC_PCU_TPC__CHIRP_PWR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x003f0000U))) /* macros for field RPT_PWR */ #define MAC_PCU_TPC__RPT_PWR__SHIFT 24 #define MAC_PCU_TPC__RPT_PWR__WIDTH 6 #define MAC_PCU_TPC__RPT_PWR__MASK 0x3f000000U #define MAC_PCU_TPC__RPT_PWR__READ(src) \ (((u_int32_t)(src)\ & 0x3f000000U) >> 24) #define MAC_PCU_TPC__RPT_PWR__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x3f000000U) #define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x3f000000U) | (((u_int32_t)(src) <<\ 24) & 0x3f000000U) #define MAC_PCU_TPC__RPT_PWR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x3f000000U))) #define MAC_PCU_TPC__TYPE u_int32_t #define MAC_PCU_TPC__READ 0x3f3f3f3fU #define MAC_PCU_TPC__WRITE 0x3f3f3f3fU #endif /* __MAC_PCU_TPC_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TPC */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TPC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_FRAME_CNT */ #ifndef __MAC_PCU_TX_FRAME_CNT_MACRO__ #define __MAC_PCU_TX_FRAME_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TX_FRAME_CNT__VALUE__SHIFT 0 #define MAC_PCU_TX_FRAME_CNT__VALUE__WIDTH 32 #define MAC_PCU_TX_FRAME_CNT__VALUE__MASK 0xffffffffU #define MAC_PCU_TX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TX_FRAME_CNT__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TX_FRAME_CNT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TX_FRAME_CNT__TYPE u_int32_t #define MAC_PCU_TX_FRAME_CNT__READ 0xffffffffU #define MAC_PCU_TX_FRAME_CNT__WRITE 0xffffffffU #endif /* __MAC_PCU_TX_FRAME_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TX_FRAME_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_FRAME_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FRAME_CNT */ #ifndef __MAC_PCU_RX_FRAME_CNT_MACRO__ #define __MAC_PCU_RX_FRAME_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_RX_FRAME_CNT__VALUE__SHIFT 0 #define MAC_PCU_RX_FRAME_CNT__VALUE__WIDTH 32 #define MAC_PCU_RX_FRAME_CNT__VALUE__MASK 0xffffffffU #define MAC_PCU_RX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_RX_FRAME_CNT__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_RX_FRAME_CNT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_RX_FRAME_CNT__TYPE u_int32_t #define MAC_PCU_RX_FRAME_CNT__READ 0xffffffffU #define MAC_PCU_RX_FRAME_CNT__WRITE 0xffffffffU #endif /* __MAC_PCU_RX_FRAME_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RX_FRAME_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FRAME_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_CNT */ #ifndef __MAC_PCU_RX_CLEAR_CNT_MACRO__ #define __MAC_PCU_RX_CLEAR_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_RX_CLEAR_CNT__VALUE__SHIFT 0 #define MAC_PCU_RX_CLEAR_CNT__VALUE__WIDTH 32 #define MAC_PCU_RX_CLEAR_CNT__VALUE__MASK 0xffffffffU #define MAC_PCU_RX_CLEAR_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_RX_CLEAR_CNT__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_RX_CLEAR_CNT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_RX_CLEAR_CNT__TYPE u_int32_t #define MAC_PCU_RX_CLEAR_CNT__READ 0xffffffffU #define MAC_PCU_RX_CLEAR_CNT__WRITE 0xffffffffU #endif /* __MAC_PCU_RX_CLEAR_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_CYCLE_CNT */ #ifndef __MAC_PCU_CYCLE_CNT_MACRO__ #define __MAC_PCU_CYCLE_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_CYCLE_CNT__VALUE__SHIFT 0 #define MAC_PCU_CYCLE_CNT__VALUE__WIDTH 32 #define MAC_PCU_CYCLE_CNT__VALUE__MASK 0xffffffffU #define MAC_PCU_CYCLE_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_CYCLE_CNT__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_CYCLE_CNT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_CYCLE_CNT__TYPE u_int32_t #define MAC_PCU_CYCLE_CNT__READ 0xffffffffU #define MAC_PCU_CYCLE_CNT__WRITE 0xffffffffU #endif /* __MAC_PCU_CYCLE_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_CYCLE_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_CYCLE_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_1 */ #ifndef __MAC_PCU_QUIET_TIME_1_MACRO__ #define __MAC_PCU_QUIET_TIME_1_MACRO__ /* macros for field ACK_CTS_ENABLE */ #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SHIFT 17 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WIDTH 1 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MASK 0x00020000U #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) #define MAC_PCU_QUIET_TIME_1__TYPE u_int32_t #define MAC_PCU_QUIET_TIME_1__READ 0x00020000U #define MAC_PCU_QUIET_TIME_1__WRITE 0x00020000U #endif /* __MAC_PCU_QUIET_TIME_1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_2 */ #ifndef __MAC_PCU_QUIET_TIME_2_MACRO__ #define __MAC_PCU_QUIET_TIME_2_MACRO__ /* macros for field DURATION */ #define MAC_PCU_QUIET_TIME_2__DURATION__SHIFT 16 #define MAC_PCU_QUIET_TIME_2__DURATION__WIDTH 16 #define MAC_PCU_QUIET_TIME_2__DURATION__MASK 0xffff0000U #define MAC_PCU_QUIET_TIME_2__DURATION__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_PCU_QUIET_TIME_2__DURATION__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_PCU_QUIET_TIME_2__DURATION__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_PCU_QUIET_TIME_2__TYPE u_int32_t #define MAC_PCU_QUIET_TIME_2__READ 0xffff0000U #define MAC_PCU_QUIET_TIME_2__WRITE 0xffff0000U #endif /* __MAC_PCU_QUIET_TIME_2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_QOS_NO_ACK */ #ifndef __MAC_PCU_QOS_NO_ACK_MACRO__ #define __MAC_PCU_QOS_NO_ACK_MACRO__ /* macros for field TWO_BIT_VALUES */ #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__SHIFT 0 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WIDTH 4 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MASK 0x0000000fU #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__READ(src) \ (u_int32_t)(src)\ & 0x0000000fU #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000000fU) #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000000fU))) /* macros for field BIT_OFFSET */ #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__SHIFT 4 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WIDTH 3 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MASK 0x00000070U #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__READ(src) \ (((u_int32_t)(src)\ & 0x00000070U) >> 4) #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000070U) #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000070U) | (((u_int32_t)(src) <<\ 4) & 0x00000070U) #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000070U))) /* macros for field BYTE_OFFSET */ #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__SHIFT 7 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WIDTH 2 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MASK 0x00000180U #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__READ(src) \ (((u_int32_t)(src)\ & 0x00000180U) >> 7) #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000180U) #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000180U) | (((u_int32_t)(src) <<\ 7) & 0x00000180U) #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000180U))) #define MAC_PCU_QOS_NO_ACK__TYPE u_int32_t #define MAC_PCU_QOS_NO_ACK__READ 0x000001ffU #define MAC_PCU_QOS_NO_ACK__WRITE 0x000001ffU #endif /* __MAC_PCU_QOS_NO_ACK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_QOS_NO_ACK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_QOS_NO_ACK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK */ #ifndef __MAC_PCU_PHY_ERROR_MASK_MACRO__ #define __MAC_PCU_PHY_ERROR_MASK_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERROR_MASK__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERROR_MASK__VALUE__WIDTH 32 #define MAC_PCU_PHY_ERROR_MASK__VALUE__MASK 0xffffffffU #define MAC_PCU_PHY_ERROR_MASK__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_PHY_ERROR_MASK__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_PHY_ERROR_MASK__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_PHY_ERROR_MASK__TYPE u_int32_t #define MAC_PCU_PHY_ERROR_MASK__READ 0xffffffffU #define MAC_PCU_PHY_ERROR_MASK__WRITE 0xffffffffU #endif /* __MAC_PCU_PHY_ERROR_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_XRLAT */ #ifndef __MAC_PCU_XRLAT_MACRO__ #define __MAC_PCU_XRLAT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_XRLAT__VALUE__SHIFT 0 #define MAC_PCU_XRLAT__VALUE__WIDTH 12 #define MAC_PCU_XRLAT__VALUE__MASK 0x00000fffU #define MAC_PCU_XRLAT__VALUE__READ(src) (u_int32_t)(src) & 0x00000fffU #define MAC_PCU_XRLAT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) #define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000fffU) | ((u_int32_t)(src) &\ 0x00000fffU) #define MAC_PCU_XRLAT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000fffU))) #define MAC_PCU_XRLAT__TYPE u_int32_t #define MAC_PCU_XRLAT__READ 0x00000fffU #define MAC_PCU_XRLAT__WRITE 0x00000fffU #endif /* __MAC_PCU_XRLAT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_XRLAT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_XRLAT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RXBUF */ #ifndef __MAC_PCU_RXBUF_MACRO__ #define __MAC_PCU_RXBUF_MACRO__ /* macros for field HIGH_PRIORITY_THRSHD */ #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__SHIFT 0 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WIDTH 11 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MASK 0x000007ffU #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__READ(src) \ (u_int32_t)(src)\ & 0x000007ffU #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WRITE(src) \ ((u_int32_t)(src)\ & 0x000007ffU) #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000007ffU) | ((u_int32_t)(src) &\ 0x000007ffU) #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000007ffU))) /* macros for field REG_RD_ENABLE */ #define MAC_PCU_RXBUF__REG_RD_ENABLE__SHIFT 11 #define MAC_PCU_RXBUF__REG_RD_ENABLE__WIDTH 1 #define MAC_PCU_RXBUF__REG_RD_ENABLE__MASK 0x00000800U #define MAC_PCU_RXBUF__REG_RD_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_RXBUF__REG_RD_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_PCU_RXBUF__REG_RD_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_PCU_RXBUF__REG_RD_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_RXBUF__REG_RD_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) #define MAC_PCU_RXBUF__TYPE u_int32_t #define MAC_PCU_RXBUF__READ 0x00000fffU #define MAC_PCU_RXBUF__WRITE 0x00000fffU #endif /* __MAC_PCU_RXBUF_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RXBUF */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RXBUF__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_CONTROL */ #ifndef __MAC_PCU_MIC_QOS_CONTROL_MACRO__ #define __MAC_PCU_MIC_QOS_CONTROL_MACRO__ /* macros for field VALUE_0 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__SHIFT 0 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MASK 0x00000003U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__READ(src) \ (u_int32_t)(src)\ & 0x00000003U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000003U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000003U) | ((u_int32_t)(src) &\ 0x00000003U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000003U))) /* macros for field VALUE_1 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__SHIFT 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MASK 0x0000000cU #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__READ(src) \ (((u_int32_t)(src)\ & 0x0000000cU) >> 2) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x0000000cU) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000cU) | (((u_int32_t)(src) <<\ 2) & 0x0000000cU) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x0000000cU))) /* macros for field VALUE_2 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__SHIFT 4 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MASK 0x00000030U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__READ(src) \ (((u_int32_t)(src)\ & 0x00000030U) >> 4) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000030U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000030U) | (((u_int32_t)(src) <<\ 4) & 0x00000030U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000030U))) /* macros for field VALUE_3 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__SHIFT 6 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MASK 0x000000c0U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__READ(src) \ (((u_int32_t)(src)\ & 0x000000c0U) >> 6) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x000000c0U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000c0U) | (((u_int32_t)(src) <<\ 6) & 0x000000c0U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x000000c0U))) /* macros for field VALUE_4 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__SHIFT 8 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MASK 0x00000300U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__READ(src) \ (((u_int32_t)(src)\ & 0x00000300U) >> 8) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000300U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000300U) | (((u_int32_t)(src) <<\ 8) & 0x00000300U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000300U))) /* macros for field VALUE_5 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__SHIFT 10 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MASK 0x00000c00U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__READ(src) \ (((u_int32_t)(src)\ & 0x00000c00U) >> 10) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000c00U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000c00U) | (((u_int32_t)(src) <<\ 10) & 0x00000c00U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000c00U))) /* macros for field VALUE_6 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__SHIFT 12 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MASK 0x00003000U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__READ(src) \ (((u_int32_t)(src)\ & 0x00003000U) >> 12) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00003000U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00003000U) | (((u_int32_t)(src) <<\ 12) & 0x00003000U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00003000U))) /* macros for field VALUE_7 */ #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__SHIFT 14 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WIDTH 2 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MASK 0x0000c000U #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__READ(src) \ (((u_int32_t)(src)\ & 0x0000c000U) >> 14) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x0000c000U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000c000U) | (((u_int32_t)(src) <<\ 14) & 0x0000c000U) #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x0000c000U))) /* macros for field ENABLE */ #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SHIFT 16 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WIDTH 1 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MASK 0x00010000U #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) #define MAC_PCU_MIC_QOS_CONTROL__TYPE u_int32_t #define MAC_PCU_MIC_QOS_CONTROL__READ 0x0001ffffU #define MAC_PCU_MIC_QOS_CONTROL__WRITE 0x0001ffffU #endif /* __MAC_PCU_MIC_QOS_CONTROL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_CONTROL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_CONTROL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_SELECT */ #ifndef __MAC_PCU_MIC_QOS_SELECT_MACRO__ #define __MAC_PCU_MIC_QOS_SELECT_MACRO__ /* macros for field VALUE_0 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__SHIFT 0 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MASK 0x0000000fU #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__READ(src) \ (u_int32_t)(src)\ & 0x0000000fU #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000000fU) #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000000fU))) /* macros for field VALUE_1 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__SHIFT 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MASK 0x000000f0U #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__READ(src) \ (((u_int32_t)(src)\ & 0x000000f0U) >> 4) #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x000000f0U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000f0U) | (((u_int32_t)(src) <<\ 4) & 0x000000f0U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x000000f0U))) /* macros for field VALUE_2 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__SHIFT 8 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MASK 0x00000f00U #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__READ(src) \ (((u_int32_t)(src)\ & 0x00000f00U) >> 8) #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000f00U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000f00U) | (((u_int32_t)(src) <<\ 8) & 0x00000f00U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000f00U))) /* macros for field VALUE_3 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__SHIFT 12 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MASK 0x0000f000U #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__READ(src) \ (((u_int32_t)(src)\ & 0x0000f000U) >> 12) #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x0000f000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000f000U) | (((u_int32_t)(src) <<\ 12) & 0x0000f000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x0000f000U))) /* macros for field VALUE_4 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__SHIFT 16 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MASK 0x000f0000U #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__READ(src) \ (((u_int32_t)(src)\ & 0x000f0000U) >> 16) #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x000f0000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000f0000U) | (((u_int32_t)(src) <<\ 16) & 0x000f0000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x000f0000U))) /* macros for field VALUE_5 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__SHIFT 20 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MASK 0x00f00000U #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__READ(src) \ (((u_int32_t)(src)\ & 0x00f00000U) >> 20) #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00f00000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00f00000U) | (((u_int32_t)(src) <<\ 20) & 0x00f00000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00f00000U))) /* macros for field VALUE_6 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__SHIFT 24 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MASK 0x0f000000U #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__READ(src) \ (((u_int32_t)(src)\ & 0x0f000000U) >> 24) #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x0f000000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0f000000U) | (((u_int32_t)(src) <<\ 24) & 0x0f000000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x0f000000U))) /* macros for field VALUE_7 */ #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__SHIFT 28 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WIDTH 4 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MASK 0xf0000000U #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__READ(src) \ (((u_int32_t)(src)\ & 0xf0000000U) >> 28) #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0xf0000000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xf0000000U) | (((u_int32_t)(src) <<\ 28) & 0xf0000000U) #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0xf0000000U))) #define MAC_PCU_MIC_QOS_SELECT__TYPE u_int32_t #define MAC_PCU_MIC_QOS_SELECT__READ 0xffffffffU #define MAC_PCU_MIC_QOS_SELECT__WRITE 0xffffffffU #endif /* __MAC_PCU_MIC_QOS_SELECT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_SELECT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_SELECT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE */ #ifndef __MAC_PCU_MISC_MODE_MACRO__ #define __MAC_PCU_MISC_MODE_MACRO__ /* macros for field BSSID_MATCH_FORCE */ #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SHIFT 0 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WIDTH 1 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MASK 0x00000001U #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field DEBUG_MODE_AD */ #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SHIFT 1 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WIDTH 1 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MASK 0x00000002U #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field MIC_NEW_LOCATION_ENABLE */ #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SHIFT 2 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MASK 0x00000004U #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field TX_ADD_TSF */ #define MAC_PCU_MISC_MODE__TX_ADD_TSF__SHIFT 3 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__WIDTH 1 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__MASK 0x00000008U #define MAC_PCU_MISC_MODE__TX_ADD_TSF__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_MISC_MODE__TX_ADD_TSF__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_MISC_MODE__TX_ADD_TSF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_MISC_MODE__TX_ADD_TSF__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_MISC_MODE__TX_ADD_TSF__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field CCK_SIFS_MODE */ #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SHIFT 4 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WIDTH 1 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MASK 0x00000010U #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field RXSM2SVD_PRE_RST */ #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SHIFT 5 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WIDTH 1 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MASK 0x00000020U #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field RCV_DELAY_SOUNDING_IM_TXBF */ #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SHIFT 6 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WIDTH 1 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MASK 0x00000040U #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field DEBUG_MODE_BA_BITMAP */ #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SHIFT 9 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WIDTH 1 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MASK 0x00000200U #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field DEBUG_MODE_SIFS */ #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SHIFT 10 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WIDTH 1 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MASK 0x00000400U #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field KC_RX_ANT_UPDATE */ #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SHIFT 11 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WIDTH 1 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MASK 0x00000800U #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field TXOP_TBTT_LIMIT_ENABLE */ #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SHIFT 12 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MASK 0x00001000U #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field MISS_BEACON_IN_SLEEP */ #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SHIFT 14 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WIDTH 1 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MASK 0x00004000U #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__READ(src) \ (((u_int32_t)(src)\ & 0x00004000U) >> 14) #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x00004000U) #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00004000U) | (((u_int32_t)(src) <<\ 14) & 0x00004000U) #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x00004000U))) #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SET(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(1) << 14) #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__CLR(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(0) << 14) /* macros for field FORCE_QUIET_COLLISION */ #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SHIFT 18 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WIDTH 1 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MASK 0x00040000U #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field BT_ANT_PREVENTS_RX */ #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SHIFT 20 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WIDTH 1 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MASK 0x00100000U #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field TBTT_PROTECT */ #define MAC_PCU_MISC_MODE__TBTT_PROTECT__SHIFT 21 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__WIDTH 1 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__MASK 0x00200000U #define MAC_PCU_MISC_MODE__TBTT_PROTECT__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_MISC_MODE__TBTT_PROTECT__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_PCU_MISC_MODE__TBTT_PROTECT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_PCU_MISC_MODE__TBTT_PROTECT__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_MISC_MODE__TBTT_PROTECT__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field HCF_POLL_CANCELS_NAV */ #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SHIFT 22 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WIDTH 1 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MASK 0x00400000U #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field RX_HCF_POLL_ENABLE */ #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SHIFT 23 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MASK 0x00800000U #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field CLEAR_VMF */ #define MAC_PCU_MISC_MODE__CLEAR_VMF__SHIFT 24 #define MAC_PCU_MISC_MODE__CLEAR_VMF__WIDTH 1 #define MAC_PCU_MISC_MODE__CLEAR_VMF__MASK 0x01000000U #define MAC_PCU_MISC_MODE__CLEAR_VMF__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_MISC_MODE__CLEAR_VMF__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_PCU_MISC_MODE__CLEAR_VMF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_PCU_MISC_MODE__CLEAR_VMF__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_MISC_MODE__CLEAR_VMF__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field CLEAR_FIRST_HCF */ #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SHIFT 25 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WIDTH 1 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MASK 0x02000000U #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) /* macros for field CLEAR_BA_VALID */ #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SHIFT 26 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WIDTH 1 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MASK 0x04000000U #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__READ(src) \ (((u_int32_t)(src)\ & 0x04000000U) >> 26) #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WRITE(src) \ (((u_int32_t)(src)\ << 26) & 0x04000000U) #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x04000000U) | (((u_int32_t)(src) <<\ 26) & 0x04000000U) #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 26) & ~0x04000000U))) #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SET(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(1) << 26) #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__CLR(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(0) << 26) /* macros for field SEL_EVM */ #define MAC_PCU_MISC_MODE__SEL_EVM__SHIFT 27 #define MAC_PCU_MISC_MODE__SEL_EVM__WIDTH 1 #define MAC_PCU_MISC_MODE__SEL_EVM__MASK 0x08000000U #define MAC_PCU_MISC_MODE__SEL_EVM__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define MAC_PCU_MISC_MODE__SEL_EVM__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define MAC_PCU_MISC_MODE__SEL_EVM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define MAC_PCU_MISC_MODE__SEL_EVM__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define MAC_PCU_MISC_MODE__SEL_EVM__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field ALWAYS_PERFORM_KEY_SEARCH */ #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SHIFT 28 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WIDTH 1 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MASK 0x10000000U #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field USE_EOP_PTR_FOR_DMA_WR */ #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SHIFT 29 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WIDTH 1 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MASK 0x20000000U #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field DEBUG_MODE */ #define MAC_PCU_MISC_MODE__DEBUG_MODE__SHIFT 30 #define MAC_PCU_MISC_MODE__DEBUG_MODE__WIDTH 2 #define MAC_PCU_MISC_MODE__DEBUG_MODE__MASK 0xc0000000U #define MAC_PCU_MISC_MODE__DEBUG_MODE__READ(src) \ (((u_int32_t)(src)\ & 0xc0000000U) >> 30) #define MAC_PCU_MISC_MODE__DEBUG_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0xc0000000U) #define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xc0000000U) | (((u_int32_t)(src) <<\ 30) & 0xc0000000U) #define MAC_PCU_MISC_MODE__DEBUG_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0xc0000000U))) #define MAC_PCU_MISC_MODE__TYPE u_int32_t #define MAC_PCU_MISC_MODE__READ 0xfff45e7fU #define MAC_PCU_MISC_MODE__WRITE 0xfff45e7fU #endif /* __MAC_PCU_MISC_MODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_OFDM_CNT */ #ifndef __MAC_PCU_FILTER_OFDM_CNT_MACRO__ #define __MAC_PCU_FILTER_OFDM_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_FILTER_OFDM_CNT__VALUE__SHIFT 0 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__WIDTH 24 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__MASK 0x00ffffffU #define MAC_PCU_FILTER_OFDM_CNT__VALUE__READ(src) \ (u_int32_t)(src)\ & 0x00ffffffU #define MAC_PCU_FILTER_OFDM_CNT__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00ffffffU) #define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_PCU_FILTER_OFDM_CNT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) #define MAC_PCU_FILTER_OFDM_CNT__TYPE u_int32_t #define MAC_PCU_FILTER_OFDM_CNT__READ 0x00ffffffU #define MAC_PCU_FILTER_OFDM_CNT__WRITE 0x00ffffffU #endif /* __MAC_PCU_FILTER_OFDM_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_FILTER_OFDM_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_OFDM_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_CCK_CNT */ #ifndef __MAC_PCU_FILTER_CCK_CNT_MACRO__ #define __MAC_PCU_FILTER_CCK_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_FILTER_CCK_CNT__VALUE__SHIFT 0 #define MAC_PCU_FILTER_CCK_CNT__VALUE__WIDTH 24 #define MAC_PCU_FILTER_CCK_CNT__VALUE__MASK 0x00ffffffU #define MAC_PCU_FILTER_CCK_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU #define MAC_PCU_FILTER_CCK_CNT__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00ffffffU) #define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_PCU_FILTER_CCK_CNT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) #define MAC_PCU_FILTER_CCK_CNT__TYPE u_int32_t #define MAC_PCU_FILTER_CCK_CNT__READ 0x00ffffffU #define MAC_PCU_FILTER_CCK_CNT__WRITE 0x00ffffffU #endif /* __MAC_PCU_FILTER_CCK_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_FILTER_CCK_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_CCK_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1 */ #ifndef __MAC_PCU_PHY_ERR_CNT_1_MACRO__ #define __MAC_PCU_PHY_ERR_CNT_1_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERR_CNT_1__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__WIDTH 24 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__MASK 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_1__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_1__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00ffffffU) #define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_PCU_PHY_ERR_CNT_1__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) #define MAC_PCU_PHY_ERR_CNT_1__TYPE u_int32_t #define MAC_PCU_PHY_ERR_CNT_1__READ 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_1__WRITE 0x00ffffffU #endif /* __MAC_PCU_PHY_ERR_CNT_1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1_MASK */ #ifndef __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ #define __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WIDTH 32 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MASK 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_PHY_ERR_CNT_1_MASK__TYPE u_int32_t #define MAC_PCU_PHY_ERR_CNT_1_MASK__READ 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_1_MASK__WRITE 0xffffffffU #endif /* __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2 */ #ifndef __MAC_PCU_PHY_ERR_CNT_2_MACRO__ #define __MAC_PCU_PHY_ERR_CNT_2_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERR_CNT_2__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__WIDTH 24 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__MASK 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_2__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_2__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00ffffffU) #define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_PCU_PHY_ERR_CNT_2__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) #define MAC_PCU_PHY_ERR_CNT_2__TYPE u_int32_t #define MAC_PCU_PHY_ERR_CNT_2__READ 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_2__WRITE 0x00ffffffU #endif /* __MAC_PCU_PHY_ERR_CNT_2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2_MASK */ #ifndef __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ #define __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WIDTH 32 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MASK 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_PHY_ERR_CNT_2_MASK__TYPE u_int32_t #define MAC_PCU_PHY_ERR_CNT_2_MASK__READ 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_2_MASK__WRITE 0xffffffffU #endif /* __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_THRESHOLD */ #ifndef __MAC_PCU_TSF_THRESHOLD_MACRO__ #define __MAC_PCU_TSF_THRESHOLD_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TSF_THRESHOLD__VALUE__SHIFT 0 #define MAC_PCU_TSF_THRESHOLD__VALUE__WIDTH 16 #define MAC_PCU_TSF_THRESHOLD__VALUE__MASK 0x0000ffffU #define MAC_PCU_TSF_THRESHOLD__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_TSF_THRESHOLD__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_TSF_THRESHOLD__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_PCU_TSF_THRESHOLD__TYPE u_int32_t #define MAC_PCU_TSF_THRESHOLD__READ 0x0000ffffU #define MAC_PCU_TSF_THRESHOLD__WRITE 0x0000ffffU #endif /* __MAC_PCU_TSF_THRESHOLD_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TSF_THRESHOLD */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_THRESHOLD__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE4 */ #ifndef __MAC_PCU_MISC_MODE4_MACRO__ #define __MAC_PCU_MISC_MODE4_MACRO__ /* macros for field EV_85395_FIX_DISABLE */ #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SHIFT 0 #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WIDTH 1 #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MASK 0x00000001U #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field MIN_AVAILABLE_FIFO_DEPTH */ #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__SHIFT 1 #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WIDTH 12 #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MASK 0x00001ffeU #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__READ(src) \ (((u_int32_t)(src)\ & 0x00001ffeU) >> 1) #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00001ffeU) #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001ffeU) | (((u_int32_t)(src) <<\ 1) & 0x00001ffeU) #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00001ffeU))) /* macros for field EV_83864_FIX_ENABLE */ #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SHIFT 13 #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MASK 0x00002000U #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00002000U) >> 13) #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 13) & 0x00002000U) #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00002000U) | (((u_int32_t)(src) <<\ 13) & 0x00002000U) #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 13) & ~0x00002000U))) #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(1) << 13) #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(0) << 13) #define MAC_PCU_MISC_MODE4__TYPE u_int32_t #define MAC_PCU_MISC_MODE4__READ 0x00003fffU #define MAC_PCU_MISC_MODE4__WRITE 0x00003fffU #endif /* __MAC_PCU_MISC_MODE4_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE4 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE4__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_EIFS_MASK */ #ifndef __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ #define __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WIDTH 32 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MASK 0xffffffffU #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_PHY_ERROR_EIFS_MASK__TYPE u_int32_t #define MAC_PCU_PHY_ERROR_EIFS_MASK__READ 0xffffffffU #define MAC_PCU_PHY_ERROR_EIFS_MASK__WRITE 0xffffffffU #endif /* __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_EIFS_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_EIFS_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3 */ #ifndef __MAC_PCU_PHY_ERR_CNT_3_MACRO__ #define __MAC_PCU_PHY_ERR_CNT_3_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERR_CNT_3__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__WIDTH 24 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__MASK 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_3__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_3__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00ffffffU) #define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ffffffU) | ((u_int32_t)(src) &\ 0x00ffffffU) #define MAC_PCU_PHY_ERR_CNT_3__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00ffffffU))) #define MAC_PCU_PHY_ERR_CNT_3__TYPE u_int32_t #define MAC_PCU_PHY_ERR_CNT_3__READ 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_3__WRITE 0x00ffffffU #endif /* __MAC_PCU_PHY_ERR_CNT_3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3_MASK */ #ifndef __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ #define __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WIDTH 32 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MASK 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_PHY_ERR_CNT_3_MASK__TYPE u_int32_t #define MAC_PCU_PHY_ERR_CNT_3_MASK__READ 0xffffffffU #define MAC_PCU_PHY_ERR_CNT_3_MASK__WRITE 0xffffffffU #endif /* __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE */ #ifndef __MAC_PCU_BLUETOOTH_MODE_MACRO__ #define __MAC_PCU_BLUETOOTH_MODE_MACRO__ /* macros for field TIME_EXTEND */ #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__SHIFT 0 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WIDTH 8 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MASK 0x000000ffU #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field TX_STATE_EXTEND */ #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SHIFT 8 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MASK 0x00000100U #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field TX_FRAME_EXTEND */ #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SHIFT 9 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MASK 0x00000200U #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field MODE */ #define MAC_PCU_BLUETOOTH_MODE__MODE__SHIFT 10 #define MAC_PCU_BLUETOOTH_MODE__MODE__WIDTH 2 #define MAC_PCU_BLUETOOTH_MODE__MODE__MASK 0x00000c00U #define MAC_PCU_BLUETOOTH_MODE__MODE__READ(src) \ (((u_int32_t)(src)\ & 0x00000c00U) >> 10) #define MAC_PCU_BLUETOOTH_MODE__MODE__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000c00U) #define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000c00U) | (((u_int32_t)(src) <<\ 10) & 0x00000c00U) #define MAC_PCU_BLUETOOTH_MODE__MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000c00U))) /* macros for field QUIET */ #define MAC_PCU_BLUETOOTH_MODE__QUIET__SHIFT 12 #define MAC_PCU_BLUETOOTH_MODE__QUIET__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE__QUIET__MASK 0x00001000U #define MAC_PCU_BLUETOOTH_MODE__QUIET__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_PCU_BLUETOOTH_MODE__QUIET__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_PCU_BLUETOOTH_MODE__QUIET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_PCU_BLUETOOTH_MODE__QUIET__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_PCU_BLUETOOTH_MODE__QUIET__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field QCU_THRESH */ #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__SHIFT 13 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WIDTH 4 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MASK 0x0001e000U #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__READ(src) \ (((u_int32_t)(src)\ & 0x0001e000U) >> 13) #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 13) & 0x0001e000U) #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0001e000U) | (((u_int32_t)(src) <<\ 13) & 0x0001e000U) #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 13) & ~0x0001e000U))) /* macros for field RX_CLEAR_POLARITY */ #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SHIFT 17 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MASK 0x00020000U #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field PRIORITY_TIME */ #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__SHIFT 18 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WIDTH 6 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MASK 0x00fc0000U #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__READ(src) \ (((u_int32_t)(src)\ & 0x00fc0000U) >> 18) #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00fc0000U) #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00fc0000U) | (((u_int32_t)(src) <<\ 18) & 0x00fc0000U) #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00fc0000U))) /* macros for field FIRST_SLOT_TIME */ #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__SHIFT 24 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WIDTH 8 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MASK 0xff000000U #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_BLUETOOTH_MODE__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_MODE__READ 0xffffffffU #define MAC_PCU_BLUETOOTH_MODE__WRITE 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_MODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */ #ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ #define __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__READ 0xffffffffU #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__WRITE 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_HCF_TIMEOUT */ #ifndef __MAC_PCU_HCF_TIMEOUT_MACRO__ #define __MAC_PCU_HCF_TIMEOUT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_HCF_TIMEOUT__VALUE__SHIFT 0 #define MAC_PCU_HCF_TIMEOUT__VALUE__WIDTH 16 #define MAC_PCU_HCF_TIMEOUT__VALUE__MASK 0x0000ffffU #define MAC_PCU_HCF_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_HCF_TIMEOUT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_HCF_TIMEOUT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_PCU_HCF_TIMEOUT__TYPE u_int32_t #define MAC_PCU_HCF_TIMEOUT__READ 0x0000ffffU #define MAC_PCU_HCF_TIMEOUT__WRITE 0x0000ffffU #endif /* __MAC_PCU_HCF_TIMEOUT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_HCF_TIMEOUT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_HCF_TIMEOUT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE2 */ #ifndef __MAC_PCU_BLUETOOTH_MODE2_MACRO__ #define __MAC_PCU_BLUETOOTH_MODE2_MACRO__ /* macros for field BCN_MISS_THRESH */ #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__SHIFT 0 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WIDTH 8 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MASK 0x000000ffU #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field BCN_MISS_CNT */ #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__SHIFT 8 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__WIDTH 8 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__MASK 0x0000ff00U #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) /* macros for field HOLD_RX_CLEAR */ #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SHIFT 16 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MASK 0x00010000U #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field SLEEP_ALLOW_BT_ACCESS */ #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SHIFT 17 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MASK 0x00020000U #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field PROTECT_BT_AFTER_WAKEUP */ #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SHIFT 19 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MASK 0x00080000U #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field DISABLE_BT_ANT */ #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SHIFT 20 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MASK 0x00100000U #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field QUIET_2_WIRE */ #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SHIFT 21 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MASK 0x00200000U #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field WL_ACTIVE_MODE */ #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__SHIFT 22 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WIDTH 2 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MASK 0x00c00000U #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__READ(src) \ (((u_int32_t)(src)\ & 0x00c00000U) >> 22) #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00c00000U) #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00c00000U) | (((u_int32_t)(src) <<\ 22) & 0x00c00000U) #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00c00000U))) /* macros for field WL_TXRX_SEPARATE */ #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SHIFT 24 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MASK 0x01000000U #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field RS_DISCARD_EXTEND */ #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SHIFT 25 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MASK 0x02000000U #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) /* macros for field TSF_BT_ACTIVE_CTRL */ #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__SHIFT 26 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WIDTH 2 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MASK 0x0c000000U #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__READ(src) \ (((u_int32_t)(src)\ & 0x0c000000U) >> 26) #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WRITE(src) \ (((u_int32_t)(src)\ << 26) & 0x0c000000U) #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0c000000U) | (((u_int32_t)(src) <<\ 26) & 0x0c000000U) #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 26) & ~0x0c000000U))) /* macros for field TSF_BT_PRIORITY_CTRL */ #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__SHIFT 28 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WIDTH 2 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MASK 0x30000000U #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__READ(src) \ (((u_int32_t)(src)\ & 0x30000000U) >> 28) #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x30000000U) #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x30000000U) | (((u_int32_t)(src) <<\ 28) & 0x30000000U) #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x30000000U))) /* macros for field INTERRUPT_ENABLE */ #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SHIFT 30 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MASK 0x40000000U #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) /* macros for field PHY_ERR_BT_COLL_ENABLE */ #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SHIFT 31 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MASK 0x80000000U #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define MAC_PCU_BLUETOOTH_MODE2__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_MODE2__READ 0xfffbffffU #define MAC_PCU_BLUETOOTH_MODE2__WRITE 0xfffbffffU #endif /* __MAC_PCU_BLUETOOTH_MODE2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2 */ #ifndef __MAC_PCU_GENERIC_TIMERS2_MACRO__ #define __MAC_PCU_GENERIC_TIMERS2_MACRO__ /* macros for field DATA */ #define MAC_PCU_GENERIC_TIMERS2__DATA__SHIFT 0 #define MAC_PCU_GENERIC_TIMERS2__DATA__WIDTH 32 #define MAC_PCU_GENERIC_TIMERS2__DATA__MASK 0xffffffffU #define MAC_PCU_GENERIC_TIMERS2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_GENERIC_TIMERS2__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_GENERIC_TIMERS2__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_GENERIC_TIMERS2__TYPE u_int32_t #define MAC_PCU_GENERIC_TIMERS2__READ 0xffffffffU #define MAC_PCU_GENERIC_TIMERS2__WRITE 0xffffffffU #endif /* __MAC_PCU_GENERIC_TIMERS2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2__NUM 16 /* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2_MODE */ #ifndef __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ #define __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ /* macros for field ENABLE */ #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__SHIFT 0 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WIDTH 8 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MASK 0x000000ffU #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field OVERFLOW_INDEX */ #define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__SHIFT 8 #define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__WIDTH 3 #define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__MASK 0x00000700U #define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__READ(src) \ (((u_int32_t)(src)\ & 0x00000700U) >> 8) #define MAC_PCU_GENERIC_TIMERS2_MODE__TYPE u_int32_t #define MAC_PCU_GENERIC_TIMERS2_MODE__READ 0x000007ffU #define MAC_PCU_GENERIC_TIMERS2_MODE__WRITE 0x000007ffU #endif /* __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2_MODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2_MODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */ #ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ #define __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__READ 0xffffffffU #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__WRITE 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */ #ifndef __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ #define __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__READ 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */ #ifndef __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ #define __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__READ 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXSIFS */ #ifndef __MAC_PCU_TXSIFS_MACRO__ #define __MAC_PCU_TXSIFS_MACRO__ /* macros for field SIFS_TIME */ #define MAC_PCU_TXSIFS__SIFS_TIME__SHIFT 0 #define MAC_PCU_TXSIFS__SIFS_TIME__WIDTH 8 #define MAC_PCU_TXSIFS__SIFS_TIME__MASK 0x000000ffU #define MAC_PCU_TXSIFS__SIFS_TIME__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_TXSIFS__SIFS_TIME__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_TXSIFS__SIFS_TIME__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field TX_LATENCY */ #define MAC_PCU_TXSIFS__TX_LATENCY__SHIFT 8 #define MAC_PCU_TXSIFS__TX_LATENCY__WIDTH 4 #define MAC_PCU_TXSIFS__TX_LATENCY__MASK 0x00000f00U #define MAC_PCU_TXSIFS__TX_LATENCY__READ(src) \ (((u_int32_t)(src)\ & 0x00000f00U) >> 8) #define MAC_PCU_TXSIFS__TX_LATENCY__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000f00U) #define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000f00U) | (((u_int32_t)(src) <<\ 8) & 0x00000f00U) #define MAC_PCU_TXSIFS__TX_LATENCY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000f00U))) /* macros for field ACK_SHIFT */ #define MAC_PCU_TXSIFS__ACK_SHIFT__SHIFT 12 #define MAC_PCU_TXSIFS__ACK_SHIFT__WIDTH 3 #define MAC_PCU_TXSIFS__ACK_SHIFT__MASK 0x00007000U #define MAC_PCU_TXSIFS__ACK_SHIFT__READ(src) \ (((u_int32_t)(src)\ & 0x00007000U) >> 12) #define MAC_PCU_TXSIFS__ACK_SHIFT__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00007000U) #define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00007000U) | (((u_int32_t)(src) <<\ 12) & 0x00007000U) #define MAC_PCU_TXSIFS__ACK_SHIFT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00007000U))) #define MAC_PCU_TXSIFS__TYPE u_int32_t #define MAC_PCU_TXSIFS__READ 0x00007fffU #define MAC_PCU_TXSIFS__WRITE 0x00007fffU #endif /* __MAC_PCU_TXSIFS_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXSIFS */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXSIFS__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE3 */ #ifndef __MAC_PCU_BLUETOOTH_MODE3_MACRO__ #define __MAC_PCU_BLUETOOTH_MODE3_MACRO__ /* macros for field WL_ACTIVE_TIME */ #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__SHIFT 0 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WIDTH 8 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MASK 0x000000ffU #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field WL_QC_TIME */ #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__SHIFT 8 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WIDTH 8 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MASK 0x0000ff00U #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field ALLOW_CONCURRENT_ACCESS */ #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__SHIFT 16 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WIDTH 4 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MASK 0x000f0000U #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__READ(src) \ (((u_int32_t)(src)\ & 0x000f0000U) >> 16) #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x000f0000U) #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000f0000U) | (((u_int32_t)(src) <<\ 16) & 0x000f0000U) #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x000f0000U))) /* macros for field AGC_SATURATION_CNT_ENABLE */ #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SHIFT 20 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WIDTH 1 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MASK 0x00100000U #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) #define MAC_PCU_BLUETOOTH_MODE3__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_MODE3__READ 0x001fffffU #define MAC_PCU_BLUETOOTH_MODE3__WRITE 0x001fffffU #endif /* __MAC_PCU_BLUETOOTH_MODE3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_X */ #ifndef __MAC_PCU_TXOP_X_MACRO__ #define __MAC_PCU_TXOP_X_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TXOP_X__VALUE__SHIFT 0 #define MAC_PCU_TXOP_X__VALUE__WIDTH 8 #define MAC_PCU_TXOP_X__VALUE__MASK 0x000000ffU #define MAC_PCU_TXOP_X__VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_TXOP_X__VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_TXOP_X__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) #define MAC_PCU_TXOP_X__TYPE u_int32_t #define MAC_PCU_TXOP_X__READ 0x000000ffU #define MAC_PCU_TXOP_X__WRITE 0x000000ffU #endif /* __MAC_PCU_TXOP_X_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXOP_X */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_X__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_0_3 */ #ifndef __MAC_PCU_TXOP_0_3_MACRO__ #define __MAC_PCU_TXOP_0_3_MACRO__ /* macros for field VALUE_0 */ #define MAC_PCU_TXOP_0_3__VALUE_0__SHIFT 0 #define MAC_PCU_TXOP_0_3__VALUE_0__WIDTH 8 #define MAC_PCU_TXOP_0_3__VALUE_0__MASK 0x000000ffU #define MAC_PCU_TXOP_0_3__VALUE_0__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_TXOP_0_3__VALUE_0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_TXOP_0_3__VALUE_0__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field VALUE_1 */ #define MAC_PCU_TXOP_0_3__VALUE_1__SHIFT 8 #define MAC_PCU_TXOP_0_3__VALUE_1__WIDTH 8 #define MAC_PCU_TXOP_0_3__VALUE_1__MASK 0x0000ff00U #define MAC_PCU_TXOP_0_3__VALUE_1__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_TXOP_0_3__VALUE_1__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_TXOP_0_3__VALUE_1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field VALUE_2 */ #define MAC_PCU_TXOP_0_3__VALUE_2__SHIFT 16 #define MAC_PCU_TXOP_0_3__VALUE_2__WIDTH 8 #define MAC_PCU_TXOP_0_3__VALUE_2__MASK 0x00ff0000U #define MAC_PCU_TXOP_0_3__VALUE_2__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_TXOP_0_3__VALUE_2__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_TXOP_0_3__VALUE_2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field VALUE_3 */ #define MAC_PCU_TXOP_0_3__VALUE_3__SHIFT 24 #define MAC_PCU_TXOP_0_3__VALUE_3__WIDTH 8 #define MAC_PCU_TXOP_0_3__VALUE_3__MASK 0xff000000U #define MAC_PCU_TXOP_0_3__VALUE_3__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_TXOP_0_3__VALUE_3__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_TXOP_0_3__VALUE_3__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_TXOP_0_3__TYPE u_int32_t #define MAC_PCU_TXOP_0_3__READ 0xffffffffU #define MAC_PCU_TXOP_0_3__WRITE 0xffffffffU #endif /* __MAC_PCU_TXOP_0_3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXOP_0_3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_0_3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_4_7 */ #ifndef __MAC_PCU_TXOP_4_7_MACRO__ #define __MAC_PCU_TXOP_4_7_MACRO__ /* macros for field VALUE_4 */ #define MAC_PCU_TXOP_4_7__VALUE_4__SHIFT 0 #define MAC_PCU_TXOP_4_7__VALUE_4__WIDTH 8 #define MAC_PCU_TXOP_4_7__VALUE_4__MASK 0x000000ffU #define MAC_PCU_TXOP_4_7__VALUE_4__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_TXOP_4_7__VALUE_4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_TXOP_4_7__VALUE_4__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field VALUE_5 */ #define MAC_PCU_TXOP_4_7__VALUE_5__SHIFT 8 #define MAC_PCU_TXOP_4_7__VALUE_5__WIDTH 8 #define MAC_PCU_TXOP_4_7__VALUE_5__MASK 0x0000ff00U #define MAC_PCU_TXOP_4_7__VALUE_5__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_TXOP_4_7__VALUE_5__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_TXOP_4_7__VALUE_5__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field VALUE_6 */ #define MAC_PCU_TXOP_4_7__VALUE_6__SHIFT 16 #define MAC_PCU_TXOP_4_7__VALUE_6__WIDTH 8 #define MAC_PCU_TXOP_4_7__VALUE_6__MASK 0x00ff0000U #define MAC_PCU_TXOP_4_7__VALUE_6__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_TXOP_4_7__VALUE_6__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_TXOP_4_7__VALUE_6__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field VALUE_7 */ #define MAC_PCU_TXOP_4_7__VALUE_7__SHIFT 24 #define MAC_PCU_TXOP_4_7__VALUE_7__WIDTH 8 #define MAC_PCU_TXOP_4_7__VALUE_7__MASK 0xff000000U #define MAC_PCU_TXOP_4_7__VALUE_7__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_TXOP_4_7__VALUE_7__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_TXOP_4_7__VALUE_7__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_TXOP_4_7__TYPE u_int32_t #define MAC_PCU_TXOP_4_7__READ 0xffffffffU #define MAC_PCU_TXOP_4_7__WRITE 0xffffffffU #endif /* __MAC_PCU_TXOP_4_7_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXOP_4_7 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_4_7__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_8_11 */ #ifndef __MAC_PCU_TXOP_8_11_MACRO__ #define __MAC_PCU_TXOP_8_11_MACRO__ /* macros for field VALUE_8 */ #define MAC_PCU_TXOP_8_11__VALUE_8__SHIFT 0 #define MAC_PCU_TXOP_8_11__VALUE_8__WIDTH 8 #define MAC_PCU_TXOP_8_11__VALUE_8__MASK 0x000000ffU #define MAC_PCU_TXOP_8_11__VALUE_8__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_TXOP_8_11__VALUE_8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_TXOP_8_11__VALUE_8__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field VALUE_9 */ #define MAC_PCU_TXOP_8_11__VALUE_9__SHIFT 8 #define MAC_PCU_TXOP_8_11__VALUE_9__WIDTH 8 #define MAC_PCU_TXOP_8_11__VALUE_9__MASK 0x0000ff00U #define MAC_PCU_TXOP_8_11__VALUE_9__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_TXOP_8_11__VALUE_9__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_TXOP_8_11__VALUE_9__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field VALUE_10 */ #define MAC_PCU_TXOP_8_11__VALUE_10__SHIFT 16 #define MAC_PCU_TXOP_8_11__VALUE_10__WIDTH 8 #define MAC_PCU_TXOP_8_11__VALUE_10__MASK 0x00ff0000U #define MAC_PCU_TXOP_8_11__VALUE_10__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_TXOP_8_11__VALUE_10__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_TXOP_8_11__VALUE_10__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field VALUE_11 */ #define MAC_PCU_TXOP_8_11__VALUE_11__SHIFT 24 #define MAC_PCU_TXOP_8_11__VALUE_11__WIDTH 8 #define MAC_PCU_TXOP_8_11__VALUE_11__MASK 0xff000000U #define MAC_PCU_TXOP_8_11__VALUE_11__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_TXOP_8_11__VALUE_11__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_TXOP_8_11__VALUE_11__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_TXOP_8_11__TYPE u_int32_t #define MAC_PCU_TXOP_8_11__READ 0xffffffffU #define MAC_PCU_TXOP_8_11__WRITE 0xffffffffU #endif /* __MAC_PCU_TXOP_8_11_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXOP_8_11 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_8_11__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_12_15 */ #ifndef __MAC_PCU_TXOP_12_15_MACRO__ #define __MAC_PCU_TXOP_12_15_MACRO__ /* macros for field VALUE_12 */ #define MAC_PCU_TXOP_12_15__VALUE_12__SHIFT 0 #define MAC_PCU_TXOP_12_15__VALUE_12__WIDTH 8 #define MAC_PCU_TXOP_12_15__VALUE_12__MASK 0x000000ffU #define MAC_PCU_TXOP_12_15__VALUE_12__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_TXOP_12_15__VALUE_12__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_TXOP_12_15__VALUE_12__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field VALUE_13 */ #define MAC_PCU_TXOP_12_15__VALUE_13__SHIFT 8 #define MAC_PCU_TXOP_12_15__VALUE_13__WIDTH 8 #define MAC_PCU_TXOP_12_15__VALUE_13__MASK 0x0000ff00U #define MAC_PCU_TXOP_12_15__VALUE_13__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_TXOP_12_15__VALUE_13__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_TXOP_12_15__VALUE_13__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field VALUE_14 */ #define MAC_PCU_TXOP_12_15__VALUE_14__SHIFT 16 #define MAC_PCU_TXOP_12_15__VALUE_14__WIDTH 8 #define MAC_PCU_TXOP_12_15__VALUE_14__MASK 0x00ff0000U #define MAC_PCU_TXOP_12_15__VALUE_14__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_TXOP_12_15__VALUE_14__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_TXOP_12_15__VALUE_14__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field VALUE_15 */ #define MAC_PCU_TXOP_12_15__VALUE_15__SHIFT 24 #define MAC_PCU_TXOP_12_15__VALUE_15__WIDTH 8 #define MAC_PCU_TXOP_12_15__VALUE_15__MASK 0xff000000U #define MAC_PCU_TXOP_12_15__VALUE_15__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_TXOP_12_15__VALUE_15__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_TXOP_12_15__VALUE_15__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_TXOP_12_15__TYPE u_int32_t #define MAC_PCU_TXOP_12_15__READ 0xffffffffU #define MAC_PCU_TXOP_12_15__WRITE 0xffffffffU #endif /* __MAC_PCU_TXOP_12_15_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXOP_12_15 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_12_15__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS */ #ifndef __MAC_PCU_GENERIC_TIMERS_MACRO__ #define __MAC_PCU_GENERIC_TIMERS_MACRO__ /* macros for field DATA */ #define MAC_PCU_GENERIC_TIMERS__DATA__SHIFT 0 #define MAC_PCU_GENERIC_TIMERS__DATA__WIDTH 32 #define MAC_PCU_GENERIC_TIMERS__DATA__MASK 0xffffffffU #define MAC_PCU_GENERIC_TIMERS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_GENERIC_TIMERS__DATA__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_GENERIC_TIMERS__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_GENERIC_TIMERS__TYPE u_int32_t #define MAC_PCU_GENERIC_TIMERS__READ 0xffffffffU #define MAC_PCU_GENERIC_TIMERS__WRITE 0xffffffffU #endif /* __MAC_PCU_GENERIC_TIMERS_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS__NUM 16 /* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS_MODE */ #ifndef __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ #define __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ /* macros for field ENABLE */ #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__SHIFT 0 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WIDTH 8 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MASK 0x000000ffU #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field OVERFLOW_INDEX */ #define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__SHIFT 8 #define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__WIDTH 3 #define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__MASK 0x00000700U #define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__READ(src) \ (((u_int32_t)(src)\ & 0x00000700U) >> 8) /* macros for field THRESH */ #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__SHIFT 12 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WIDTH 20 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MASK 0xfffff000U #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__READ(src) \ (((u_int32_t)(src)\ & 0xfffff000U) >> 12) #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0xfffff000U) #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xfffff000U) | (((u_int32_t)(src) <<\ 12) & 0xfffff000U) #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0xfffff000U))) #define MAC_PCU_GENERIC_TIMERS_MODE__TYPE u_int32_t #define MAC_PCU_GENERIC_TIMERS_MODE__READ 0xfffff7ffU #define MAC_PCU_GENERIC_TIMERS_MODE__WRITE 0xfffff7ffU #endif /* __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS_MODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS_MODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_MODE */ #ifndef __MAC_PCU_SLP32_MODE_MACRO__ #define __MAC_PCU_SLP32_MODE_MACRO__ /* macros for field HALF_CLK_LATENCY */ #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__SHIFT 0 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WIDTH 20 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MASK 0x000fffffU #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__READ(src) \ (u_int32_t)(src)\ & 0x000fffffU #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WRITE(src) \ ((u_int32_t)(src)\ & 0x000fffffU) #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000fffffU) | ((u_int32_t)(src) &\ 0x000fffffU) #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000fffffU))) /* macros for field ENABLE */ #define MAC_PCU_SLP32_MODE__ENABLE__SHIFT 20 #define MAC_PCU_SLP32_MODE__ENABLE__WIDTH 1 #define MAC_PCU_SLP32_MODE__ENABLE__MASK 0x00100000U #define MAC_PCU_SLP32_MODE__ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_SLP32_MODE__ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_SLP32_MODE__ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_SLP32_MODE__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_SLP32_MODE__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field TSF_WRITE_STATUS */ #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SHIFT 21 #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__WIDTH 1 #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__MASK 0x00200000U #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field DISABLE_32KHZ */ #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SHIFT 22 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WIDTH 1 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MASK 0x00400000U #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field FORCE_BIAS_BLOCK_ON */ #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SHIFT 23 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WIDTH 1 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MASK 0x00800000U #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field TSF2_WRITE_STATUS */ #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SHIFT 24 #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__WIDTH 1 #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__MASK 0x01000000U #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) #define MAC_PCU_SLP32_MODE__TYPE u_int32_t #define MAC_PCU_SLP32_MODE__READ 0x01ffffffU #define MAC_PCU_SLP32_MODE__WRITE 0x01ffffffU #endif /* __MAC_PCU_SLP32_MODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP32_MODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_MODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_WAKE */ #ifndef __MAC_PCU_SLP32_WAKE_MACRO__ #define __MAC_PCU_SLP32_WAKE_MACRO__ /* macros for field XTL_TIME */ #define MAC_PCU_SLP32_WAKE__XTL_TIME__SHIFT 0 #define MAC_PCU_SLP32_WAKE__XTL_TIME__WIDTH 16 #define MAC_PCU_SLP32_WAKE__XTL_TIME__MASK 0x0000ffffU #define MAC_PCU_SLP32_WAKE__XTL_TIME__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_SLP32_WAKE__XTL_TIME__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_SLP32_WAKE__XTL_TIME__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_PCU_SLP32_WAKE__TYPE u_int32_t #define MAC_PCU_SLP32_WAKE__READ 0x0000ffffU #define MAC_PCU_SLP32_WAKE__WRITE 0x0000ffffU #endif /* __MAC_PCU_SLP32_WAKE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP32_WAKE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_WAKE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_INC */ #ifndef __MAC_PCU_SLP32_INC_MACRO__ #define __MAC_PCU_SLP32_INC_MACRO__ /* macros for field TSF_INC */ #define MAC_PCU_SLP32_INC__TSF_INC__SHIFT 0 #define MAC_PCU_SLP32_INC__TSF_INC__WIDTH 20 #define MAC_PCU_SLP32_INC__TSF_INC__MASK 0x000fffffU #define MAC_PCU_SLP32_INC__TSF_INC__READ(src) (u_int32_t)(src) & 0x000fffffU #define MAC_PCU_SLP32_INC__TSF_INC__WRITE(src) ((u_int32_t)(src) & 0x000fffffU) #define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000fffffU) | ((u_int32_t)(src) &\ 0x000fffffU) #define MAC_PCU_SLP32_INC__TSF_INC__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000fffffU))) #define MAC_PCU_SLP32_INC__TYPE u_int32_t #define MAC_PCU_SLP32_INC__READ 0x000fffffU #define MAC_PCU_SLP32_INC__WRITE 0x000fffffU #endif /* __MAC_PCU_SLP32_INC_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP32_INC */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_INC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB1 */ #ifndef __MAC_PCU_SLP_MIB1_MACRO__ #define __MAC_PCU_SLP_MIB1_MACRO__ /* macros for field SLEEP_CNT */ #define MAC_PCU_SLP_MIB1__SLEEP_CNT__SHIFT 0 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__WIDTH 32 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__MASK 0xffffffffU #define MAC_PCU_SLP_MIB1__SLEEP_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_SLP_MIB1__SLEEP_CNT__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_SLP_MIB1__SLEEP_CNT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_SLP_MIB1__TYPE u_int32_t #define MAC_PCU_SLP_MIB1__READ 0xffffffffU #define MAC_PCU_SLP_MIB1__WRITE 0xffffffffU #endif /* __MAC_PCU_SLP_MIB1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB2 */ #ifndef __MAC_PCU_SLP_MIB2_MACRO__ #define __MAC_PCU_SLP_MIB2_MACRO__ /* macros for field CYCLE_CNT */ #define MAC_PCU_SLP_MIB2__CYCLE_CNT__SHIFT 0 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__WIDTH 32 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__MASK 0xffffffffU #define MAC_PCU_SLP_MIB2__CYCLE_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_SLP_MIB2__CYCLE_CNT__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_SLP_MIB2__CYCLE_CNT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_SLP_MIB2__TYPE u_int32_t #define MAC_PCU_SLP_MIB2__READ 0xffffffffU #define MAC_PCU_SLP_MIB2__WRITE 0xffffffffU #endif /* __MAC_PCU_SLP_MIB2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB3 */ #ifndef __MAC_PCU_SLP_MIB3_MACRO__ #define __MAC_PCU_SLP_MIB3_MACRO__ /* macros for field CLR_CNT */ #define MAC_PCU_SLP_MIB3__CLR_CNT__SHIFT 0 #define MAC_PCU_SLP_MIB3__CLR_CNT__WIDTH 1 #define MAC_PCU_SLP_MIB3__CLR_CNT__MASK 0x00000001U #define MAC_PCU_SLP_MIB3__CLR_CNT__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_SLP_MIB3__CLR_CNT__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_SLP_MIB3__CLR_CNT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_SLP_MIB3__CLR_CNT__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_SLP_MIB3__CLR_CNT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field PENDING */ #define MAC_PCU_SLP_MIB3__PENDING__SHIFT 1 #define MAC_PCU_SLP_MIB3__PENDING__WIDTH 1 #define MAC_PCU_SLP_MIB3__PENDING__MASK 0x00000002U #define MAC_PCU_SLP_MIB3__PENDING__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_SLP_MIB3__PENDING__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_SLP_MIB3__PENDING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) #define MAC_PCU_SLP_MIB3__TYPE u_int32_t #define MAC_PCU_SLP_MIB3__READ 0x00000003U #define MAC_PCU_SLP_MIB3__WRITE 0x00000003U #endif /* __MAC_PCU_SLP_MIB3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW1 */ #ifndef __MAC_PCU_WOW1_MACRO__ #define __MAC_PCU_WOW1_MACRO__ /* macros for field PATTERN_ENABLE */ #define MAC_PCU_WOW1__PATTERN_ENABLE__SHIFT 0 #define MAC_PCU_WOW1__PATTERN_ENABLE__WIDTH 8 #define MAC_PCU_WOW1__PATTERN_ENABLE__MASK 0x000000ffU #define MAC_PCU_WOW1__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_WOW1__PATTERN_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_WOW1__PATTERN_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field PATTERN_DETECT */ #define MAC_PCU_WOW1__PATTERN_DETECT__SHIFT 8 #define MAC_PCU_WOW1__PATTERN_DETECT__WIDTH 8 #define MAC_PCU_WOW1__PATTERN_DETECT__MASK 0x0000ff00U #define MAC_PCU_WOW1__PATTERN_DETECT__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) /* macros for field MAGIC_ENABLE */ #define MAC_PCU_WOW1__MAGIC_ENABLE__SHIFT 16 #define MAC_PCU_WOW1__MAGIC_ENABLE__WIDTH 1 #define MAC_PCU_WOW1__MAGIC_ENABLE__MASK 0x00010000U #define MAC_PCU_WOW1__MAGIC_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_WOW1__MAGIC_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_WOW1__MAGIC_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_WOW1__MAGIC_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_WOW1__MAGIC_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field MAGIC_DETECT */ #define MAC_PCU_WOW1__MAGIC_DETECT__SHIFT 17 #define MAC_PCU_WOW1__MAGIC_DETECT__WIDTH 1 #define MAC_PCU_WOW1__MAGIC_DETECT__MASK 0x00020000U #define MAC_PCU_WOW1__MAGIC_DETECT__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_WOW1__MAGIC_DETECT__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_WOW1__MAGIC_DETECT__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field INTR_ENABLE */ #define MAC_PCU_WOW1__INTR_ENABLE__SHIFT 18 #define MAC_PCU_WOW1__INTR_ENABLE__WIDTH 1 #define MAC_PCU_WOW1__INTR_ENABLE__MASK 0x00040000U #define MAC_PCU_WOW1__INTR_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_PCU_WOW1__INTR_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_PCU_WOW1__INTR_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_PCU_WOW1__INTR_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_PCU_WOW1__INTR_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field INTR_DETECT */ #define MAC_PCU_WOW1__INTR_DETECT__SHIFT 19 #define MAC_PCU_WOW1__INTR_DETECT__WIDTH 1 #define MAC_PCU_WOW1__INTR_DETECT__MASK 0x00080000U #define MAC_PCU_WOW1__INTR_DETECT__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_WOW1__INTR_DETECT__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_WOW1__INTR_DETECT__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field KEEP_ALIVE_FAIL */ #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SHIFT 20 #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__WIDTH 1 #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__MASK 0x00100000U #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field BEACON_FAIL */ #define MAC_PCU_WOW1__BEACON_FAIL__SHIFT 21 #define MAC_PCU_WOW1__BEACON_FAIL__WIDTH 1 #define MAC_PCU_WOW1__BEACON_FAIL__MASK 0x00200000U #define MAC_PCU_WOW1__BEACON_FAIL__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_WOW1__BEACON_FAIL__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_WOW1__BEACON_FAIL__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field CW_BITS */ #define MAC_PCU_WOW1__CW_BITS__SHIFT 28 #define MAC_PCU_WOW1__CW_BITS__WIDTH 4 #define MAC_PCU_WOW1__CW_BITS__MASK 0xf0000000U #define MAC_PCU_WOW1__CW_BITS__READ(src) \ (((u_int32_t)(src)\ & 0xf0000000U) >> 28) #define MAC_PCU_WOW1__CW_BITS__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0xf0000000U) #define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xf0000000U) | (((u_int32_t)(src) <<\ 28) & 0xf0000000U) #define MAC_PCU_WOW1__CW_BITS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0xf0000000U))) #define MAC_PCU_WOW1__TYPE u_int32_t #define MAC_PCU_WOW1__READ 0xf03fffffU #define MAC_PCU_WOW1__WRITE 0xf03fffffU #endif /* __MAC_PCU_WOW1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW2 */ #ifndef __MAC_PCU_WOW2_MACRO__ #define __MAC_PCU_WOW2_MACRO__ /* macros for field AIFS */ #define MAC_PCU_WOW2__AIFS__SHIFT 0 #define MAC_PCU_WOW2__AIFS__WIDTH 8 #define MAC_PCU_WOW2__AIFS__MASK 0x000000ffU #define MAC_PCU_WOW2__AIFS__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_WOW2__AIFS__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_WOW2__AIFS__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) /* macros for field SLOT */ #define MAC_PCU_WOW2__SLOT__SHIFT 8 #define MAC_PCU_WOW2__SLOT__WIDTH 8 #define MAC_PCU_WOW2__SLOT__MASK 0x0000ff00U #define MAC_PCU_WOW2__SLOT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define MAC_PCU_WOW2__SLOT__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) #define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_WOW2__SLOT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field TRY_CNT */ #define MAC_PCU_WOW2__TRY_CNT__SHIFT 16 #define MAC_PCU_WOW2__TRY_CNT__WIDTH 8 #define MAC_PCU_WOW2__TRY_CNT__MASK 0x00ff0000U #define MAC_PCU_WOW2__TRY_CNT__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_WOW2__TRY_CNT__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_WOW2__TRY_CNT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) #define MAC_PCU_WOW2__TYPE u_int32_t #define MAC_PCU_WOW2__READ 0x00ffffffU #define MAC_PCU_WOW2__WRITE 0x00ffffffU #endif /* __MAC_PCU_WOW2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER */ #ifndef __MAC_PCU_LOGIC_ANALYZER_MACRO__ #define __MAC_PCU_LOGIC_ANALYZER_MACRO__ /* macros for field HOLD */ #define MAC_PCU_LOGIC_ANALYZER__HOLD__SHIFT 0 #define MAC_PCU_LOGIC_ANALYZER__HOLD__WIDTH 1 #define MAC_PCU_LOGIC_ANALYZER__HOLD__MASK 0x00000001U #define MAC_PCU_LOGIC_ANALYZER__HOLD__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_LOGIC_ANALYZER__HOLD__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_LOGIC_ANALYZER__HOLD__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_LOGIC_ANALYZER__HOLD__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_LOGIC_ANALYZER__HOLD__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field CLEAR */ #define MAC_PCU_LOGIC_ANALYZER__CLEAR__SHIFT 1 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__WIDTH 1 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__MASK 0x00000002U #define MAC_PCU_LOGIC_ANALYZER__CLEAR__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_LOGIC_ANALYZER__CLEAR__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_LOGIC_ANALYZER__CLEAR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_LOGIC_ANALYZER__CLEAR__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_LOGIC_ANALYZER__CLEAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field STATE */ #define MAC_PCU_LOGIC_ANALYZER__STATE__SHIFT 2 #define MAC_PCU_LOGIC_ANALYZER__STATE__WIDTH 1 #define MAC_PCU_LOGIC_ANALYZER__STATE__MASK 0x00000004U #define MAC_PCU_LOGIC_ANALYZER__STATE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_LOGIC_ANALYZER__STATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_LOGIC_ANALYZER__STATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field ENABLE */ #define MAC_PCU_LOGIC_ANALYZER__ENABLE__SHIFT 3 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__WIDTH 1 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__MASK 0x00000008U #define MAC_PCU_LOGIC_ANALYZER__ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_LOGIC_ANALYZER__ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_LOGIC_ANALYZER__ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_LOGIC_ANALYZER__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_LOGIC_ANALYZER__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field QCU_SEL */ #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__SHIFT 4 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WIDTH 4 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MASK 0x000000f0U #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x000000f0U) >> 4) #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x000000f0U) #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000f0U) | (((u_int32_t)(src) <<\ 4) & 0x000000f0U) #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x000000f0U))) /* macros for field INT_ADDR */ #define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__SHIFT 8 #define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__WIDTH 10 #define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__MASK 0x0003ff00U #define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__READ(src) \ (((u_int32_t)(src)\ & 0x0003ff00U) >> 8) /* macros for field DIAG_MODE */ #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__SHIFT 18 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WIDTH 14 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MASK 0xfffc0000U #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__READ(src) \ (((u_int32_t)(src)\ & 0xfffc0000U) >> 18) #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0xfffc0000U) #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xfffc0000U) | (((u_int32_t)(src) <<\ 18) & 0xfffc0000U) #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0xfffc0000U))) #define MAC_PCU_LOGIC_ANALYZER__TYPE u_int32_t #define MAC_PCU_LOGIC_ANALYZER__READ 0xffffffffU #define MAC_PCU_LOGIC_ANALYZER__WRITE 0xffffffffU #endif /* __MAC_PCU_LOGIC_ANALYZER_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_32L */ #ifndef __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ #define __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ /* macros for field MASK */ #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__SHIFT 0 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WIDTH 32 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MASK 0xffffffffU #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_LOGIC_ANALYZER_32L__TYPE u_int32_t #define MAC_PCU_LOGIC_ANALYZER_32L__READ 0xffffffffU #define MAC_PCU_LOGIC_ANALYZER_32L__WRITE 0xffffffffU #endif /* __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_32L */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_32L__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_16U */ #ifndef __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ #define __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ /* macros for field MASK */ #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__SHIFT 0 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WIDTH 16 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MASK 0x0000ffffU #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_PCU_LOGIC_ANALYZER_16U__TYPE u_int32_t #define MAC_PCU_LOGIC_ANALYZER_16U__READ 0x0000ffffU #define MAC_PCU_LOGIC_ANALYZER_16U__WRITE 0x0000ffffU #endif /* __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_16U */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_16U__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON_FAIL */ #ifndef __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ #define __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ /* macros for field ENABLE */ #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SHIFT 0 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WIDTH 1 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MASK 0x00000001U #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) #define MAC_PCU_WOW3_BEACON_FAIL__TYPE u_int32_t #define MAC_PCU_WOW3_BEACON_FAIL__READ 0x00000001U #define MAC_PCU_WOW3_BEACON_FAIL__WRITE 0x00000001U #endif /* __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON_FAIL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON_FAIL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON */ #ifndef __MAC_PCU_WOW3_BEACON_MACRO__ #define __MAC_PCU_WOW3_BEACON_MACRO__ /* macros for field TIMEOUT */ #define MAC_PCU_WOW3_BEACON__TIMEOUT__SHIFT 0 #define MAC_PCU_WOW3_BEACON__TIMEOUT__WIDTH 32 #define MAC_PCU_WOW3_BEACON__TIMEOUT__MASK 0xffffffffU #define MAC_PCU_WOW3_BEACON__TIMEOUT__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_WOW3_BEACON__TIMEOUT__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_WOW3_BEACON__TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_WOW3_BEACON__TYPE u_int32_t #define MAC_PCU_WOW3_BEACON__READ 0xffffffffU #define MAC_PCU_WOW3_BEACON__WRITE 0xffffffffU #endif /* __MAC_PCU_WOW3_BEACON_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_KEEP_ALIVE */ #ifndef __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ #define __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ /* macros for field TIMEOUT */ #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__SHIFT 0 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WIDTH 32 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MASK 0xffffffffU #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_WOW3_KEEP_ALIVE__TYPE u_int32_t #define MAC_PCU_WOW3_KEEP_ALIVE__READ 0xffffffffU #define MAC_PCU_WOW3_KEEP_ALIVE__WRITE 0xffffffffU #endif /* __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW3_KEEP_ALIVE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_KEEP_ALIVE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_KA */ #ifndef __MAC_PCU_WOW_KA_MACRO__ #define __MAC_PCU_WOW_KA_MACRO__ /* macros for field AUTO_DISABLE */ #define MAC_PCU_WOW_KA__AUTO_DISABLE__SHIFT 0 #define MAC_PCU_WOW_KA__AUTO_DISABLE__WIDTH 1 #define MAC_PCU_WOW_KA__AUTO_DISABLE__MASK 0x00000001U #define MAC_PCU_WOW_KA__AUTO_DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_WOW_KA__AUTO_DISABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_WOW_KA__AUTO_DISABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_WOW_KA__AUTO_DISABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_WOW_KA__AUTO_DISABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field FAIL_DISABLE */ #define MAC_PCU_WOW_KA__FAIL_DISABLE__SHIFT 1 #define MAC_PCU_WOW_KA__FAIL_DISABLE__WIDTH 1 #define MAC_PCU_WOW_KA__FAIL_DISABLE__MASK 0x00000002U #define MAC_PCU_WOW_KA__FAIL_DISABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_WOW_KA__FAIL_DISABLE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_WOW_KA__FAIL_DISABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_WOW_KA__FAIL_DISABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_WOW_KA__FAIL_DISABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field BKOFF_CS_ENABLE */ #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SHIFT 2 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WIDTH 1 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MASK 0x00000004U #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) #define MAC_PCU_WOW_KA__TYPE u_int32_t #define MAC_PCU_WOW_KA__READ 0x00000007U #define MAC_PCU_WOW_KA__WRITE 0x00000007U #endif /* __MAC_PCU_WOW_KA_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW_KA */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_KA__NUM 1 /* macros for BlueprintGlobalNameSpace::PCU_1US */ #ifndef __PCU_1US_MACRO__ #define __PCU_1US_MACRO__ /* macros for field SCALER */ #define PCU_1US__SCALER__SHIFT 0 #define PCU_1US__SCALER__WIDTH 7 #define PCU_1US__SCALER__MASK 0x0000007fU #define PCU_1US__SCALER__READ(src) (u_int32_t)(src) & 0x0000007fU #define PCU_1US__SCALER__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) #define PCU_1US__SCALER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000007fU) | ((u_int32_t)(src) &\ 0x0000007fU) #define PCU_1US__SCALER__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) #define PCU_1US__TYPE u_int32_t #define PCU_1US__READ 0x0000007fU #define PCU_1US__WRITE 0x0000007fU #endif /* __PCU_1US_MACRO__ */ /* macros for mac_pcu_reg_map.PCU_1US */ #define INST_MAC_PCU_REG_MAP__PCU_1US__NUM 1 /* macros for BlueprintGlobalNameSpace::PCU_KA */ #ifndef __PCU_KA_MACRO__ #define __PCU_KA_MACRO__ /* macros for field DEL */ #define PCU_KA__DEL__SHIFT 0 #define PCU_KA__DEL__WIDTH 12 #define PCU_KA__DEL__MASK 0x00000fffU #define PCU_KA__DEL__READ(src) (u_int32_t)(src) & 0x00000fffU #define PCU_KA__DEL__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) #define PCU_KA__DEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000fffU) | ((u_int32_t)(src) &\ 0x00000fffU) #define PCU_KA__DEL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000fffU))) #define PCU_KA__TYPE u_int32_t #define PCU_KA__READ 0x00000fffU #define PCU_KA__WRITE 0x00000fffU #endif /* __PCU_KA_MACRO__ */ /* macros for mac_pcu_reg_map.PCU_KA */ #define INST_MAC_PCU_REG_MAP__PCU_KA__NUM 1 /* macros for BlueprintGlobalNameSpace::WOW_EXACT */ #ifndef __WOW_EXACT_MACRO__ #define __WOW_EXACT_MACRO__ /* macros for field LENGTH */ #define WOW_EXACT__LENGTH__SHIFT 0 #define WOW_EXACT__LENGTH__WIDTH 8 #define WOW_EXACT__LENGTH__MASK 0x000000ffU #define WOW_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU #define WOW_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define WOW_EXACT__LENGTH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define WOW_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) /* macros for field OFFSET */ #define WOW_EXACT__OFFSET__SHIFT 8 #define WOW_EXACT__OFFSET__WIDTH 8 #define WOW_EXACT__OFFSET__MASK 0x0000ff00U #define WOW_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define WOW_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) #define WOW_EXACT__OFFSET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define WOW_EXACT__OFFSET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) #define WOW_EXACT__TYPE u_int32_t #define WOW_EXACT__READ 0x0000ffffU #define WOW_EXACT__WRITE 0x0000ffffU #endif /* __WOW_EXACT_MACRO__ */ /* macros for mac_pcu_reg_map.WOW_EXACT */ #define INST_MAC_PCU_REG_MAP__WOW_EXACT__NUM 1 /* macros for BlueprintGlobalNameSpace::PCU_WOW4 */ #ifndef __PCU_WOW4_MACRO__ #define __PCU_WOW4_MACRO__ /* macros for field OFFSET0 */ #define PCU_WOW4__OFFSET0__SHIFT 0 #define PCU_WOW4__OFFSET0__WIDTH 8 #define PCU_WOW4__OFFSET0__MASK 0x000000ffU #define PCU_WOW4__OFFSET0__READ(src) (u_int32_t)(src) & 0x000000ffU #define PCU_WOW4__OFFSET0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define PCU_WOW4__OFFSET0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define PCU_WOW4__OFFSET0__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) /* macros for field OFFSET1 */ #define PCU_WOW4__OFFSET1__SHIFT 8 #define PCU_WOW4__OFFSET1__WIDTH 8 #define PCU_WOW4__OFFSET1__MASK 0x0000ff00U #define PCU_WOW4__OFFSET1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define PCU_WOW4__OFFSET1__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) #define PCU_WOW4__OFFSET1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define PCU_WOW4__OFFSET1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field OFFSET2 */ #define PCU_WOW4__OFFSET2__SHIFT 16 #define PCU_WOW4__OFFSET2__WIDTH 8 #define PCU_WOW4__OFFSET2__MASK 0x00ff0000U #define PCU_WOW4__OFFSET2__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) #define PCU_WOW4__OFFSET2__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) #define PCU_WOW4__OFFSET2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define PCU_WOW4__OFFSET2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field OFFSET3 */ #define PCU_WOW4__OFFSET3__SHIFT 24 #define PCU_WOW4__OFFSET3__WIDTH 8 #define PCU_WOW4__OFFSET3__MASK 0xff000000U #define PCU_WOW4__OFFSET3__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) #define PCU_WOW4__OFFSET3__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) #define PCU_WOW4__OFFSET3__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define PCU_WOW4__OFFSET3__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define PCU_WOW4__TYPE u_int32_t #define PCU_WOW4__READ 0xffffffffU #define PCU_WOW4__WRITE 0xffffffffU #endif /* __PCU_WOW4_MACRO__ */ /* macros for mac_pcu_reg_map.PCU_WOW4 */ #define INST_MAC_PCU_REG_MAP__PCU_WOW4__NUM 1 /* macros for BlueprintGlobalNameSpace::PCU_WOW5 */ #ifndef __PCU_WOW5_MACRO__ #define __PCU_WOW5_MACRO__ /* macros for field OFFSET4 */ #define PCU_WOW5__OFFSET4__SHIFT 0 #define PCU_WOW5__OFFSET4__WIDTH 8 #define PCU_WOW5__OFFSET4__MASK 0x000000ffU #define PCU_WOW5__OFFSET4__READ(src) (u_int32_t)(src) & 0x000000ffU #define PCU_WOW5__OFFSET4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define PCU_WOW5__OFFSET4__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define PCU_WOW5__OFFSET4__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) /* macros for field OFFSET5 */ #define PCU_WOW5__OFFSET5__SHIFT 8 #define PCU_WOW5__OFFSET5__WIDTH 8 #define PCU_WOW5__OFFSET5__MASK 0x0000ff00U #define PCU_WOW5__OFFSET5__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define PCU_WOW5__OFFSET5__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) #define PCU_WOW5__OFFSET5__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define PCU_WOW5__OFFSET5__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field OFFSET6 */ #define PCU_WOW5__OFFSET6__SHIFT 16 #define PCU_WOW5__OFFSET6__WIDTH 8 #define PCU_WOW5__OFFSET6__MASK 0x00ff0000U #define PCU_WOW5__OFFSET6__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) #define PCU_WOW5__OFFSET6__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) #define PCU_WOW5__OFFSET6__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define PCU_WOW5__OFFSET6__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field OFFSET7 */ #define PCU_WOW5__OFFSET7__SHIFT 24 #define PCU_WOW5__OFFSET7__WIDTH 8 #define PCU_WOW5__OFFSET7__MASK 0xff000000U #define PCU_WOW5__OFFSET7__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) #define PCU_WOW5__OFFSET7__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) #define PCU_WOW5__OFFSET7__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define PCU_WOW5__OFFSET7__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define PCU_WOW5__TYPE u_int32_t #define PCU_WOW5__READ 0xffffffffU #define PCU_WOW5__WRITE 0xffffffffU #endif /* __PCU_WOW5_MACRO__ */ /* macros for mac_pcu_reg_map.PCU_WOW5 */ #define INST_MAC_PCU_REG_MAP__PCU_WOW5__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_MASK_CONT */ #ifndef __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ #define __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ /* macros for field MASK1 */ #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__SHIFT 0 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WIDTH 8 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MASK 0x000000ffU #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field MASK2 */ #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__SHIFT 8 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WIDTH 8 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MASK 0x0000ff00U #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field MASK3 */ #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__SHIFT 16 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WIDTH 8 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MASK 0x00ff0000U #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__TYPE u_int32_t #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__READ 0x00ffffffU #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__WRITE 0x00ffffffU #endif /* __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_MASK_CONT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_MASK_CONT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_MODE */ #ifndef __MAC_PCU_AZIMUTH_MODE_MACRO__ #define __MAC_PCU_AZIMUTH_MODE_MACRO__ /* macros for field DISABLE_TSF_UPDATE */ #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SHIFT 0 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MASK 0x00000001U #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field KEY_SEARCH_AD1 */ #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SHIFT 1 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MASK 0x00000002U #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field TX_TSF_STATUS_SEL */ #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SHIFT 2 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MASK 0x00000004U #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field RX_TSF_STATUS_SEL */ #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SHIFT 3 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MASK 0x00000008U #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field CLK_EN */ #define MAC_PCU_AZIMUTH_MODE__CLK_EN__SHIFT 4 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__MASK 0x00000010U #define MAC_PCU_AZIMUTH_MODE__CLK_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_AZIMUTH_MODE__CLK_EN__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_AZIMUTH_MODE__CLK_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_AZIMUTH_MODE__CLK_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_AZIMUTH_MODE__CLK_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field TX_DESC_EN */ #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SHIFT 5 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MASK 0x00000020U #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field ACK_CTS_MATCH_TX_AD2 */ #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SHIFT 6 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MASK 0x00000040U #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field BA_USES_AD1 */ #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SHIFT 7 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MASK 0x00000080U #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field WMAC_CLK_SEL */ #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SHIFT 8 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MASK 0x00000100U #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field FILTER_PASS_HOLD */ #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SHIFT 9 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MASK 0x00000200U #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field PROXY_STA_FIX1_ENABLE */ #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SHIFT 10 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MASK 0x00000400U #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field PROXY_STA_FIX2_ENABLE */ #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SHIFT 11 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MASK 0x00000800U #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field PROXY_STA_FIX3_ENABLE */ #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SHIFT 12 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WIDTH 1 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MASK 0x00001000U #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) #define MAC_PCU_AZIMUTH_MODE__TYPE u_int32_t #define MAC_PCU_AZIMUTH_MODE__READ 0x00001fffU #define MAC_PCU_AZIMUTH_MODE__WRITE 0x00001fffU #endif /* __MAC_PCU_AZIMUTH_MODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_MODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_MODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_TIME_STAMP */ #ifndef __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ #define __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ /* macros for field VALUE */ #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__SHIFT 0 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WIDTH 32 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MASK 0xffffffffU #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_AZIMUTH_TIME_STAMP__TYPE u_int32_t #define MAC_PCU_AZIMUTH_TIME_STAMP__READ 0xffffffffU #define MAC_PCU_AZIMUTH_TIME_STAMP__WRITE 0xffffffffU #endif /* __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_TIME_STAMP */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_TIME_STAMP__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_20_40_MODE */ #ifndef __MAC_PCU_20_40_MODE_MACRO__ #define __MAC_PCU_20_40_MODE_MACRO__ /* macros for field JOINED_RX_CLEAR */ #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SHIFT 0 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WIDTH 1 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MASK 0x00000001U #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field EXT_PIFS_ENABLE */ #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SHIFT 1 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WIDTH 1 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MASK 0x00000002U #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field TX_HT20_ON_EXT_BUSY */ #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SHIFT 2 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WIDTH 1 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MASK 0x00000004U #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field SWAMPED_FORCES_RX_CLEAR_CTL_IDLE */ #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SHIFT 3 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WIDTH 1 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MASK 0x00000008U #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field PIFS_CYCLES */ #define MAC_PCU_20_40_MODE__PIFS_CYCLES__SHIFT 4 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__WIDTH 12 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__MASK 0x0000fff0U #define MAC_PCU_20_40_MODE__PIFS_CYCLES__READ(src) \ (((u_int32_t)(src)\ & 0x0000fff0U) >> 4) #define MAC_PCU_20_40_MODE__PIFS_CYCLES__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x0000fff0U) #define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000fff0U) | (((u_int32_t)(src) <<\ 4) & 0x0000fff0U) #define MAC_PCU_20_40_MODE__PIFS_CYCLES__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x0000fff0U))) #define MAC_PCU_20_40_MODE__TYPE u_int32_t #define MAC_PCU_20_40_MODE__READ 0x0000ffffU #define MAC_PCU_20_40_MODE__WRITE 0x0000ffffU #endif /* __MAC_PCU_20_40_MODE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_20_40_MODE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_20_40_MODE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_H_XFER_TIMEOUT */ #ifndef __MAC_PCU_H_XFER_TIMEOUT_MACRO__ #define __MAC_PCU_H_XFER_TIMEOUT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_H_XFER_TIMEOUT__VALUE__SHIFT 0 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__WIDTH 5 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__MASK 0x0000001fU #define MAC_PCU_H_XFER_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000001fU #define MAC_PCU_H_XFER_TIMEOUT__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000001fU) #define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000001fU) | ((u_int32_t)(src) &\ 0x0000001fU) #define MAC_PCU_H_XFER_TIMEOUT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000001fU))) /* macros for field DISABLE */ #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SHIFT 5 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WIDTH 1 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MASK 0x00000020U #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field EXTXBF_IMMEDIATE_RESP */ #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SHIFT 6 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WIDTH 1 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MASK 0x00000040U #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field DELAY_EXTXBF_ONLY_UPLOAD_H */ #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SHIFT 7 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WIDTH 1 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MASK 0x00000080U #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field EXTXBF_NOACK_NORPT */ #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SHIFT 8 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WIDTH 1 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MASK 0x00000100U #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) #define MAC_PCU_H_XFER_TIMEOUT__TYPE u_int32_t #define MAC_PCU_H_XFER_TIMEOUT__READ 0x000001ffU #define MAC_PCU_H_XFER_TIMEOUT__WRITE 0x000001ffU #endif /* __MAC_PCU_H_XFER_TIMEOUT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_H_XFER_TIMEOUT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_H_XFER_TIMEOUT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_DIFF_CNT */ #ifndef __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ #define __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ /* macros for field VALUE */ #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__SHIFT 0 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WIDTH 32 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MASK 0xffffffffU #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_RX_CLEAR_DIFF_CNT__TYPE u_int32_t #define MAC_PCU_RX_CLEAR_DIFF_CNT__READ 0xffffffffU #define MAC_PCU_RX_CLEAR_DIFF_CNT__WRITE 0xffffffffU #endif /* __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_DIFF_CNT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_DIFF_CNT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_ANTENNA_MASK */ #ifndef __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ #define __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ /* macros for field VALUE */ #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__SHIFT 0 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WIDTH 3 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MASK 0x00000007U #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__READ(src) \ (u_int32_t)(src)\ & 0x00000007U #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000007U) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000007U) | ((u_int32_t)(src) &\ 0x00000007U) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000007U))) /* macros for field ONE_RESP_EN */ #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SHIFT 3 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WIDTH 1 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MASK 0x00000008U #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field FORCE_CHAIN_0 */ #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SHIFT 4 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WIDTH 1 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MASK 0x00000010U #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) #define MAC_PCU_SELF_GEN_ANTENNA_MASK__TYPE u_int32_t #define MAC_PCU_SELF_GEN_ANTENNA_MASK__READ 0x0000001fU #define MAC_PCU_SELF_GEN_ANTENNA_MASK__WRITE 0x0000001fU #endif /* __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_ANTENNA_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_ANTENNA_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BA_BAR_CONTROL */ #ifndef __MAC_PCU_BA_BAR_CONTROL_MACRO__ #define __MAC_PCU_BA_BAR_CONTROL_MACRO__ /* macros for field COMPRESSED_OFFSET */ #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__SHIFT 0 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WIDTH 4 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MASK 0x0000000fU #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__READ(src) \ (u_int32_t)(src)\ & 0x0000000fU #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000000fU) #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000000fU) | ((u_int32_t)(src) &\ 0x0000000fU) #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000000fU))) /* macros for field ACK_POLICY_OFFSET */ #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__SHIFT 4 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WIDTH 4 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MASK 0x000000f0U #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__READ(src) \ (((u_int32_t)(src)\ & 0x000000f0U) >> 4) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x000000f0U) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000f0U) | (((u_int32_t)(src) <<\ 4) & 0x000000f0U) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x000000f0U))) /* macros for field COMPRESSED_VALUE */ #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SHIFT 8 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WIDTH 1 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MASK 0x00000100U #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field ACK_POLICY_VALUE */ #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SHIFT 9 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WIDTH 1 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MASK 0x00000200U #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field FORCE_NO_MATCH */ #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SHIFT 10 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WIDTH 1 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MASK 0x00000400U #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field TX_BA_CLEAR_BA_VALID */ #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SHIFT 11 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WIDTH 1 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MASK 0x00000800U #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field UPDATE_BA_BITMAP_QOS_NULL */ #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SHIFT 12 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WIDTH 1 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MASK 0x00001000U #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) #define MAC_PCU_BA_BAR_CONTROL__TYPE u_int32_t #define MAC_PCU_BA_BAR_CONTROL__READ 0x00001fffU #define MAC_PCU_BA_BAR_CONTROL__WRITE 0x00001fffU #endif /* __MAC_PCU_BA_BAR_CONTROL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BA_BAR_CONTROL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BA_BAR_CONTROL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_LEGACY_PLCP_SPOOF */ #ifndef __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ #define __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ /* macros for field EIFS_MINUS_DIFS */ #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__SHIFT 0 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WIDTH 8 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MASK 0x000000ffU #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field MIN_LENGTH */ #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__SHIFT 8 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WIDTH 5 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MASK 0x00001f00U #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__READ(src) \ (((u_int32_t)(src)\ & 0x00001f00U) >> 8) #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00001f00U) #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001f00U) | (((u_int32_t)(src) <<\ 8) & 0x00001f00U) #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00001f00U))) #define MAC_PCU_LEGACY_PLCP_SPOOF__TYPE u_int32_t #define MAC_PCU_LEGACY_PLCP_SPOOF__READ 0x00001fffU #define MAC_PCU_LEGACY_PLCP_SPOOF__WRITE 0x00001fffU #endif /* __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_LEGACY_PLCP_SPOOF */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_LEGACY_PLCP_SPOOF__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK_CONT */ #ifndef __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ #define __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ /* macros for field MASK_VALUE */ #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__SHIFT 0 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WIDTH 8 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MASK 0x000000ffU #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field EIFS_VALUE */ #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__SHIFT 16 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WIDTH 8 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MASK 0x00ff0000U #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field AIFS_VALUE */ #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__SHIFT 24 #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WIDTH 8 #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MASK 0xff000000U #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_PHY_ERROR_MASK_CONT__TYPE u_int32_t #define MAC_PCU_PHY_ERROR_MASK_CONT__READ 0xffff00ffU #define MAC_PCU_PHY_ERROR_MASK_CONT__WRITE 0xffff00ffU #endif /* __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK_CONT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK_CONT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_TIMER */ #ifndef __MAC_PCU_TX_TIMER_MACRO__ #define __MAC_PCU_TX_TIMER_MACRO__ /* macros for field TX_TIMER */ #define MAC_PCU_TX_TIMER__TX_TIMER__SHIFT 0 #define MAC_PCU_TX_TIMER__TX_TIMER__WIDTH 15 #define MAC_PCU_TX_TIMER__TX_TIMER__MASK 0x00007fffU #define MAC_PCU_TX_TIMER__TX_TIMER__READ(src) (u_int32_t)(src) & 0x00007fffU #define MAC_PCU_TX_TIMER__TX_TIMER__WRITE(src) ((u_int32_t)(src) & 0x00007fffU) #define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00007fffU) | ((u_int32_t)(src) &\ 0x00007fffU) #define MAC_PCU_TX_TIMER__TX_TIMER__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00007fffU))) /* macros for field TX_TIMER_ENABLE */ #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SHIFT 15 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WIDTH 1 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MASK 0x00008000U #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00008000U) >> 15) #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 15) & 0x00008000U) #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00008000U) | (((u_int32_t)(src) <<\ 15) & 0x00008000U) #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 15) & ~0x00008000U))) #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(1) << 15) #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(0) << 15) /* macros for field RIFS_TIMER */ #define MAC_PCU_TX_TIMER__RIFS_TIMER__SHIFT 16 #define MAC_PCU_TX_TIMER__RIFS_TIMER__WIDTH 4 #define MAC_PCU_TX_TIMER__RIFS_TIMER__MASK 0x000f0000U #define MAC_PCU_TX_TIMER__RIFS_TIMER__READ(src) \ (((u_int32_t)(src)\ & 0x000f0000U) >> 16) #define MAC_PCU_TX_TIMER__RIFS_TIMER__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x000f0000U) #define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000f0000U) | (((u_int32_t)(src) <<\ 16) & 0x000f0000U) #define MAC_PCU_TX_TIMER__RIFS_TIMER__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x000f0000U))) /* macros for field QUIET_TIMER */ #define MAC_PCU_TX_TIMER__QUIET_TIMER__SHIFT 20 #define MAC_PCU_TX_TIMER__QUIET_TIMER__WIDTH 5 #define MAC_PCU_TX_TIMER__QUIET_TIMER__MASK 0x01f00000U #define MAC_PCU_TX_TIMER__QUIET_TIMER__READ(src) \ (((u_int32_t)(src)\ & 0x01f00000U) >> 20) #define MAC_PCU_TX_TIMER__QUIET_TIMER__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x01f00000U) #define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01f00000U) | (((u_int32_t)(src) <<\ 20) & 0x01f00000U) #define MAC_PCU_TX_TIMER__QUIET_TIMER__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x01f00000U))) /* macros for field QUIET_TIMER_ENABLE */ #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SHIFT 25 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WIDTH 1 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MASK 0x02000000U #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) #define MAC_PCU_TX_TIMER__TYPE u_int32_t #define MAC_PCU_TX_TIMER__READ 0x03ffffffU #define MAC_PCU_TX_TIMER__WRITE 0x03ffffffU #endif /* __MAC_PCU_TX_TIMER_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TX_TIMER */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_TIMER__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_CTRL */ #ifndef __MAC_PCU_TXBUF_CTRL_MACRO__ #define __MAC_PCU_TXBUF_CTRL_MACRO__ /* macros for field USABLE_ENTRIES */ #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__SHIFT 0 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WIDTH 12 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MASK 0x00000fffU #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__READ(src) \ (u_int32_t)(src)\ & 0x00000fffU #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000fffU) #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000fffU) | ((u_int32_t)(src) &\ 0x00000fffU) #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000fffU))) /* macros for field TX_FIFO_WRAP_ENABLE */ #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SHIFT 16 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WIDTH 1 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MASK 0x00010000U #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) #define MAC_PCU_TXBUF_CTRL__TYPE u_int32_t #define MAC_PCU_TXBUF_CTRL__READ 0x00010fffU #define MAC_PCU_TXBUF_CTRL__WRITE 0x00010fffU #endif /* __MAC_PCU_TXBUF_CTRL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_CTRL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_CTRL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE2 */ #ifndef __MAC_PCU_MISC_MODE2_MACRO__ #define __MAC_PCU_MISC_MODE2_MACRO__ /* macros for field BUG_21532_FIX_ENABLE */ #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SHIFT 0 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MASK 0x00000001U #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field MGMT_CRYPTO_ENABLE */ #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SHIFT 1 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MASK 0x00000002U #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field NO_CRYPTO_FOR_NON_DATA_PKT */ #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SHIFT 2 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WIDTH 1 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MASK 0x00000004U #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field BUG_58603_FIX_ENABLE */ #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SHIFT 3 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MASK 0x00000008U #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field BUG_58057_FIX_ENABLE */ #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SHIFT 4 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MASK 0x00000010U #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field RESERVED_0 */ #define MAC_PCU_MISC_MODE2__RESERVED_0__SHIFT 5 #define MAC_PCU_MISC_MODE2__RESERVED_0__WIDTH 1 #define MAC_PCU_MISC_MODE2__RESERVED_0__MASK 0x00000020U #define MAC_PCU_MISC_MODE2__RESERVED_0__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_MISC_MODE2__RESERVED_0__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_MISC_MODE2__RESERVED_0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_MISC_MODE2__RESERVED_0__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_MISC_MODE2__RESERVED_0__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field ADHOC_MCAST_KEYID_ENABLE */ #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SHIFT 6 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MASK 0x00000040U #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field CFP_IGNORE */ #define MAC_PCU_MISC_MODE2__CFP_IGNORE__SHIFT 7 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__WIDTH 1 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__MASK 0x00000080U #define MAC_PCU_MISC_MODE2__CFP_IGNORE__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_MISC_MODE2__CFP_IGNORE__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_MISC_MODE2__CFP_IGNORE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_MISC_MODE2__CFP_IGNORE__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_MISC_MODE2__CFP_IGNORE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field MGMT_QOS */ #define MAC_PCU_MISC_MODE2__MGMT_QOS__SHIFT 8 #define MAC_PCU_MISC_MODE2__MGMT_QOS__WIDTH 8 #define MAC_PCU_MISC_MODE2__MGMT_QOS__MASK 0x0000ff00U #define MAC_PCU_MISC_MODE2__MGMT_QOS__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_MISC_MODE2__MGMT_QOS__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_MISC_MODE2__MGMT_QOS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field ENABLE_LOAD_NAV_BEACON_DURATION */ #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SHIFT 16 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WIDTH 1 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MASK 0x00010000U #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field AGG_WEP */ #define MAC_PCU_MISC_MODE2__AGG_WEP__SHIFT 17 #define MAC_PCU_MISC_MODE2__AGG_WEP__WIDTH 1 #define MAC_PCU_MISC_MODE2__AGG_WEP__MASK 0x00020000U #define MAC_PCU_MISC_MODE2__AGG_WEP__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_MISC_MODE2__AGG_WEP__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_MISC_MODE2__AGG_WEP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_MISC_MODE2__AGG_WEP__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_MISC_MODE2__AGG_WEP__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field BC_MC_WAPI_MODE */ #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SHIFT 18 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WIDTH 1 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MASK 0x00040000U #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field DUR_ACCOUNT_BY_BA */ #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SHIFT 19 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WIDTH 1 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MASK 0x00080000U #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field BUG_28676 */ #define MAC_PCU_MISC_MODE2__BUG_28676__SHIFT 20 #define MAC_PCU_MISC_MODE2__BUG_28676__WIDTH 1 #define MAC_PCU_MISC_MODE2__BUG_28676__MASK 0x00100000U #define MAC_PCU_MISC_MODE2__BUG_28676__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_MISC_MODE2__BUG_28676__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_MISC_MODE2__BUG_28676__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_MISC_MODE2__BUG_28676__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_MISC_MODE2__BUG_28676__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field CLEAR_MORE_FRAG */ #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SHIFT 21 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WIDTH 1 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MASK 0x00200000U #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field IGNORE_TXOP_1ST_PKT */ #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SHIFT 22 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WIDTH 1 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MASK 0x00400000U #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field MPDU_DENSITY_STS_FIX */ #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SHIFT 23 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WIDTH 1 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MASK 0x00800000U #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field MPDU_DENSITY_WAIT_WEP */ #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SHIFT 24 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WIDTH 1 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MASK 0x01000000U #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field RCV_TIMESTAMP_FIX */ #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SHIFT 25 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WIDTH 1 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MASK 0x02000000U #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__READ(src) \ (((u_int32_t)(src)\ & 0x02000000U) >> 25) #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x02000000U) #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x02000000U) | (((u_int32_t)(src) <<\ 25) & 0x02000000U) #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x02000000U))) #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SET(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(1) << 25) #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__CLR(dst) \ (dst) = ((dst) &\ ~0x02000000U) | ((u_int32_t)(0) << 25) /* macros for field PM_FIELD_FOR_NON_CTRL */ #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SHIFT 26 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WIDTH 1 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MASK 0x04000000U #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__READ(src) \ (((u_int32_t)(src)\ & 0x04000000U) >> 26) #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WRITE(src) \ (((u_int32_t)(src)\ << 26) & 0x04000000U) #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x04000000U) | (((u_int32_t)(src) <<\ 26) & 0x04000000U) #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 26) & ~0x04000000U))) #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SET(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(1) << 26) #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__CLR(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(0) << 26) /* macros for field DECOUPLE_DECRYPTION */ #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SHIFT 27 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WIDTH 1 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MASK 0x08000000U #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field H_TO_SW_DEBUG_MODE */ #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SHIFT 28 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WIDTH 1 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MASK 0x10000000U #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field TXBF_ACT_RPT_DONE_PASS */ #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SHIFT 29 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WIDTH 1 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MASK 0x20000000U #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field PCU_LOOP_TXBF */ #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SHIFT 30 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WIDTH 1 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MASK 0x40000000U #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) /* macros for field CLEAR_WEP_TXBUSY_ON_TXURN */ #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SHIFT 31 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WIDTH 1 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MASK 0x80000000U #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define MAC_PCU_MISC_MODE2__TYPE u_int32_t #define MAC_PCU_MISC_MODE2__READ 0xffffffffU #define MAC_PCU_MISC_MODE2__WRITE 0xffffffffU #endif /* __MAC_PCU_MISC_MODE2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_ALT_AES_MUTE_MASK */ #ifndef __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ #define __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ /* macros for field QOS */ #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__SHIFT 16 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WIDTH 16 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MASK 0xffff0000U #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__READ(src) \ (((u_int32_t)(src)\ & 0xffff0000U) >> 16) #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0xffff0000U) #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffff0000U) | (((u_int32_t)(src) <<\ 16) & 0xffff0000U) #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0xffff0000U))) #define MAC_PCU_ALT_AES_MUTE_MASK__TYPE u_int32_t #define MAC_PCU_ALT_AES_MUTE_MASK__READ 0xffff0000U #define MAC_PCU_ALT_AES_MUTE_MASK__WRITE 0xffff0000U #endif /* __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_ALT_AES_MUTE_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_ALT_AES_MUTE_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW6 */ #ifndef __MAC_PCU_WOW6_MACRO__ #define __MAC_PCU_WOW6_MACRO__ /* macros for field RXBUF_START_ADDR */ #define MAC_PCU_WOW6__RXBUF_START_ADDR__SHIFT 0 #define MAC_PCU_WOW6__RXBUF_START_ADDR__WIDTH 16 #define MAC_PCU_WOW6__RXBUF_START_ADDR__MASK 0x0000ffffU #define MAC_PCU_WOW6__RXBUF_START_ADDR__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define MAC_PCU_WOW6__TYPE u_int32_t #define MAC_PCU_WOW6__READ 0x0000ffffU #endif /* __MAC_PCU_WOW6_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW6 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW6__NUM 1 /* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG1 */ #ifndef __ASYNC_FIFO_REG1_MACRO__ #define __ASYNC_FIFO_REG1_MACRO__ /* macros for field DBG */ #define ASYNC_FIFO_REG1__DBG__SHIFT 0 #define ASYNC_FIFO_REG1__DBG__WIDTH 30 #define ASYNC_FIFO_REG1__DBG__MASK 0x3fffffffU #define ASYNC_FIFO_REG1__DBG__READ(src) (u_int32_t)(src) & 0x3fffffffU #define ASYNC_FIFO_REG1__DBG__WRITE(src) ((u_int32_t)(src) & 0x3fffffffU) #define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x3fffffffU) | ((u_int32_t)(src) &\ 0x3fffffffU) #define ASYNC_FIFO_REG1__DBG__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x3fffffffU))) #define ASYNC_FIFO_REG1__TYPE u_int32_t #define ASYNC_FIFO_REG1__READ 0x3fffffffU #define ASYNC_FIFO_REG1__WRITE 0x3fffffffU #endif /* __ASYNC_FIFO_REG1_MACRO__ */ /* macros for mac_pcu_reg_map.ASYNC_FIFO_REG1 */ #define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG1__NUM 1 /* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG2 */ #ifndef __ASYNC_FIFO_REG2_MACRO__ #define __ASYNC_FIFO_REG2_MACRO__ /* macros for field DBG */ #define ASYNC_FIFO_REG2__DBG__SHIFT 0 #define ASYNC_FIFO_REG2__DBG__WIDTH 28 #define ASYNC_FIFO_REG2__DBG__MASK 0x0fffffffU #define ASYNC_FIFO_REG2__DBG__READ(src) (u_int32_t)(src) & 0x0fffffffU #define ASYNC_FIFO_REG2__DBG__WRITE(src) ((u_int32_t)(src) & 0x0fffffffU) #define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0fffffffU) | ((u_int32_t)(src) &\ 0x0fffffffU) #define ASYNC_FIFO_REG2__DBG__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0fffffffU))) #define ASYNC_FIFO_REG2__TYPE u_int32_t #define ASYNC_FIFO_REG2__READ 0x0fffffffU #define ASYNC_FIFO_REG2__WRITE 0x0fffffffU #endif /* __ASYNC_FIFO_REG2_MACRO__ */ /* macros for mac_pcu_reg_map.ASYNC_FIFO_REG2 */ #define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG2__NUM 1 /* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG3 */ #ifndef __ASYNC_FIFO_REG3_MACRO__ #define __ASYNC_FIFO_REG3_MACRO__ /* macros for field DBG */ #define ASYNC_FIFO_REG3__DBG__SHIFT 0 #define ASYNC_FIFO_REG3__DBG__WIDTH 10 #define ASYNC_FIFO_REG3__DBG__MASK 0x000003ffU #define ASYNC_FIFO_REG3__DBG__READ(src) (u_int32_t)(src) & 0x000003ffU #define ASYNC_FIFO_REG3__DBG__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) #define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000003ffU) | ((u_int32_t)(src) &\ 0x000003ffU) #define ASYNC_FIFO_REG3__DBG__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000003ffU))) /* macros for field DATAPATH_SEL */ #define ASYNC_FIFO_REG3__DATAPATH_SEL__SHIFT 10 #define ASYNC_FIFO_REG3__DATAPATH_SEL__WIDTH 1 #define ASYNC_FIFO_REG3__DATAPATH_SEL__MASK 0x00000400U #define ASYNC_FIFO_REG3__DATAPATH_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define ASYNC_FIFO_REG3__DATAPATH_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define ASYNC_FIFO_REG3__DATAPATH_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define ASYNC_FIFO_REG3__DATAPATH_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define ASYNC_FIFO_REG3__DATAPATH_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field SFT_RST_N */ #define ASYNC_FIFO_REG3__SFT_RST_N__SHIFT 31 #define ASYNC_FIFO_REG3__SFT_RST_N__WIDTH 1 #define ASYNC_FIFO_REG3__SFT_RST_N__MASK 0x80000000U #define ASYNC_FIFO_REG3__SFT_RST_N__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define ASYNC_FIFO_REG3__SFT_RST_N__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define ASYNC_FIFO_REG3__SFT_RST_N__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define ASYNC_FIFO_REG3__SFT_RST_N__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define ASYNC_FIFO_REG3__SFT_RST_N__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define ASYNC_FIFO_REG3__TYPE u_int32_t #define ASYNC_FIFO_REG3__READ 0x800007ffU #define ASYNC_FIFO_REG3__WRITE 0x800007ffU #endif /* __ASYNC_FIFO_REG3_MACRO__ */ /* macros for mac_pcu_reg_map.ASYNC_FIFO_REG3 */ #define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW5 */ #ifndef __MAC_PCU_WOW5_MACRO__ #define __MAC_PCU_WOW5_MACRO__ /* macros for field RX_ABORT_ENABLE */ #define MAC_PCU_WOW5__RX_ABORT_ENABLE__SHIFT 0 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__WIDTH 16 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__MASK 0x0000ffffU #define MAC_PCU_WOW5__RX_ABORT_ENABLE__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_WOW5__RX_ABORT_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_WOW5__RX_ABORT_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define MAC_PCU_WOW5__TYPE u_int32_t #define MAC_PCU_WOW5__READ 0x0000ffffU #define MAC_PCU_WOW5__WRITE 0x0000ffffU #endif /* __MAC_PCU_WOW5_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW5 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW5__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH1 */ #ifndef __MAC_PCU_WOW_LENGTH1_MACRO__ #define __MAC_PCU_WOW_LENGTH1_MACRO__ /* macros for field PATTERN_3 */ #define MAC_PCU_WOW_LENGTH1__PATTERN_3__SHIFT 0 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__WIDTH 8 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__MASK 0x000000ffU #define MAC_PCU_WOW_LENGTH1__PATTERN_3__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_WOW_LENGTH1__PATTERN_3__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_WOW_LENGTH1__PATTERN_3__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field PATTERN_2 */ #define MAC_PCU_WOW_LENGTH1__PATTERN_2__SHIFT 8 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__WIDTH 8 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__MASK 0x0000ff00U #define MAC_PCU_WOW_LENGTH1__PATTERN_2__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_WOW_LENGTH1__PATTERN_2__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH1__PATTERN_2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field PATTERN_1 */ #define MAC_PCU_WOW_LENGTH1__PATTERN_1__SHIFT 16 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__WIDTH 8 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__MASK 0x00ff0000U #define MAC_PCU_WOW_LENGTH1__PATTERN_1__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_WOW_LENGTH1__PATTERN_1__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH1__PATTERN_1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field PATTERN_0 */ #define MAC_PCU_WOW_LENGTH1__PATTERN_0__SHIFT 24 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__WIDTH 8 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__MASK 0xff000000U #define MAC_PCU_WOW_LENGTH1__PATTERN_0__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_WOW_LENGTH1__PATTERN_0__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH1__PATTERN_0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_WOW_LENGTH1__TYPE u_int32_t #define MAC_PCU_WOW_LENGTH1__READ 0xffffffffU #define MAC_PCU_WOW_LENGTH1__WRITE 0xffffffffU #endif /* __MAC_PCU_WOW_LENGTH1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH2 */ #ifndef __MAC_PCU_WOW_LENGTH2_MACRO__ #define __MAC_PCU_WOW_LENGTH2_MACRO__ /* macros for field PATTERN_7 */ #define MAC_PCU_WOW_LENGTH2__PATTERN_7__SHIFT 0 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__WIDTH 8 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__MASK 0x000000ffU #define MAC_PCU_WOW_LENGTH2__PATTERN_7__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_WOW_LENGTH2__PATTERN_7__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_WOW_LENGTH2__PATTERN_7__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field PATTERN_6 */ #define MAC_PCU_WOW_LENGTH2__PATTERN_6__SHIFT 8 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__WIDTH 8 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__MASK 0x0000ff00U #define MAC_PCU_WOW_LENGTH2__PATTERN_6__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_WOW_LENGTH2__PATTERN_6__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH2__PATTERN_6__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field PATTERN_5 */ #define MAC_PCU_WOW_LENGTH2__PATTERN_5__SHIFT 16 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__WIDTH 8 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__MASK 0x00ff0000U #define MAC_PCU_WOW_LENGTH2__PATTERN_5__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_WOW_LENGTH2__PATTERN_5__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH2__PATTERN_5__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field PATTERN_4 */ #define MAC_PCU_WOW_LENGTH2__PATTERN_4__SHIFT 24 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__WIDTH 8 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__MASK 0xff000000U #define MAC_PCU_WOW_LENGTH2__PATTERN_4__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_WOW_LENGTH2__PATTERN_4__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH2__PATTERN_4__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_WOW_LENGTH2__TYPE u_int32_t #define MAC_PCU_WOW_LENGTH2__READ 0xffffffffU #define MAC_PCU_WOW_LENGTH2__WRITE 0xffffffffU #endif /* __MAC_PCU_WOW_LENGTH2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH2__NUM 1 /* macros for BlueprintGlobalNameSpace::WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */ #ifndef __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ #define __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ /* macros for field EN */ #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__SHIFT 0 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WIDTH 16 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MASK 0x0000ffffU #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__READ(src) \ (u_int32_t)(src)\ & 0x0000ffffU #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WRITE(src) \ ((u_int32_t)(src)\ & 0x0000ffffU) #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__TYPE u_int32_t #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__READ 0x0000ffffU #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__WRITE 0x0000ffffU #endif /* __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ */ /* macros for mac_pcu_reg_map.WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */ #define INST_MAC_PCU_REG_MAP__WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW4 */ #ifndef __MAC_PCU_WOW4_MACRO__ #define __MAC_PCU_WOW4_MACRO__ /* macros for field PATTERN_ENABLE */ #define MAC_PCU_WOW4__PATTERN_ENABLE__SHIFT 0 #define MAC_PCU_WOW4__PATTERN_ENABLE__WIDTH 8 #define MAC_PCU_WOW4__PATTERN_ENABLE__MASK 0x000000ffU #define MAC_PCU_WOW4__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU #define MAC_PCU_WOW4__PATTERN_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_WOW4__PATTERN_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field PATTERN_DETECT */ #define MAC_PCU_WOW4__PATTERN_DETECT__SHIFT 8 #define MAC_PCU_WOW4__PATTERN_DETECT__WIDTH 8 #define MAC_PCU_WOW4__PATTERN_DETECT__MASK 0x0000ff00U #define MAC_PCU_WOW4__PATTERN_DETECT__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_WOW4__TYPE u_int32_t #define MAC_PCU_WOW4__READ 0x0000ffffU #define MAC_PCU_WOW4__WRITE 0x0000ffffU #endif /* __MAC_PCU_WOW4_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW4 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW4__NUM 1 /* macros for BlueprintGlobalNameSpace::WOW2_EXACT */ #ifndef __WOW2_EXACT_MACRO__ #define __WOW2_EXACT_MACRO__ /* macros for field LENGTH */ #define WOW2_EXACT__LENGTH__SHIFT 0 #define WOW2_EXACT__LENGTH__WIDTH 8 #define WOW2_EXACT__LENGTH__MASK 0x000000ffU #define WOW2_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU #define WOW2_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define WOW2_EXACT__LENGTH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define WOW2_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) /* macros for field OFFSET */ #define WOW2_EXACT__OFFSET__SHIFT 8 #define WOW2_EXACT__OFFSET__WIDTH 8 #define WOW2_EXACT__OFFSET__MASK 0x0000ff00U #define WOW2_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define WOW2_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) #define WOW2_EXACT__OFFSET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define WOW2_EXACT__OFFSET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) #define WOW2_EXACT__TYPE u_int32_t #define WOW2_EXACT__READ 0x0000ffffU #define WOW2_EXACT__WRITE 0x0000ffffU #endif /* __WOW2_EXACT_MACRO__ */ /* macros for mac_pcu_reg_map.WOW2_EXACT */ #define INST_MAC_PCU_REG_MAP__WOW2_EXACT__NUM 1 /* macros for BlueprintGlobalNameSpace::PCU_WOW6 */ #ifndef __PCU_WOW6_MACRO__ #define __PCU_WOW6_MACRO__ /* macros for field OFFSET8 */ #define PCU_WOW6__OFFSET8__SHIFT 0 #define PCU_WOW6__OFFSET8__WIDTH 8 #define PCU_WOW6__OFFSET8__MASK 0x000000ffU #define PCU_WOW6__OFFSET8__READ(src) (u_int32_t)(src) & 0x000000ffU #define PCU_WOW6__OFFSET8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define PCU_WOW6__OFFSET8__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define PCU_WOW6__OFFSET8__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) /* macros for field OFFSET9 */ #define PCU_WOW6__OFFSET9__SHIFT 8 #define PCU_WOW6__OFFSET9__WIDTH 8 #define PCU_WOW6__OFFSET9__MASK 0x0000ff00U #define PCU_WOW6__OFFSET9__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define PCU_WOW6__OFFSET9__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) #define PCU_WOW6__OFFSET9__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define PCU_WOW6__OFFSET9__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field OFFSET10 */ #define PCU_WOW6__OFFSET10__SHIFT 16 #define PCU_WOW6__OFFSET10__WIDTH 8 #define PCU_WOW6__OFFSET10__MASK 0x00ff0000U #define PCU_WOW6__OFFSET10__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) #define PCU_WOW6__OFFSET10__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) #define PCU_WOW6__OFFSET10__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define PCU_WOW6__OFFSET10__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field OFFSET11 */ #define PCU_WOW6__OFFSET11__SHIFT 24 #define PCU_WOW6__OFFSET11__WIDTH 8 #define PCU_WOW6__OFFSET11__MASK 0xff000000U #define PCU_WOW6__OFFSET11__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) #define PCU_WOW6__OFFSET11__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) #define PCU_WOW6__OFFSET11__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define PCU_WOW6__OFFSET11__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define PCU_WOW6__TYPE u_int32_t #define PCU_WOW6__READ 0xffffffffU #define PCU_WOW6__WRITE 0xffffffffU #endif /* __PCU_WOW6_MACRO__ */ /* macros for mac_pcu_reg_map.PCU_WOW6 */ #define INST_MAC_PCU_REG_MAP__PCU_WOW6__NUM 1 /* macros for BlueprintGlobalNameSpace::PCU_WOW7 */ #ifndef __PCU_WOW7_MACRO__ #define __PCU_WOW7_MACRO__ /* macros for field OFFSET12 */ #define PCU_WOW7__OFFSET12__SHIFT 0 #define PCU_WOW7__OFFSET12__WIDTH 8 #define PCU_WOW7__OFFSET12__MASK 0x000000ffU #define PCU_WOW7__OFFSET12__READ(src) (u_int32_t)(src) & 0x000000ffU #define PCU_WOW7__OFFSET12__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) #define PCU_WOW7__OFFSET12__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define PCU_WOW7__OFFSET12__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) /* macros for field OFFSET13 */ #define PCU_WOW7__OFFSET13__SHIFT 8 #define PCU_WOW7__OFFSET13__WIDTH 8 #define PCU_WOW7__OFFSET13__MASK 0x0000ff00U #define PCU_WOW7__OFFSET13__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) #define PCU_WOW7__OFFSET13__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) #define PCU_WOW7__OFFSET13__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define PCU_WOW7__OFFSET13__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field OFFSET14 */ #define PCU_WOW7__OFFSET14__SHIFT 16 #define PCU_WOW7__OFFSET14__WIDTH 8 #define PCU_WOW7__OFFSET14__MASK 0x00ff0000U #define PCU_WOW7__OFFSET14__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) #define PCU_WOW7__OFFSET14__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) #define PCU_WOW7__OFFSET14__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define PCU_WOW7__OFFSET14__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field OFFSET15 */ #define PCU_WOW7__OFFSET15__SHIFT 24 #define PCU_WOW7__OFFSET15__WIDTH 8 #define PCU_WOW7__OFFSET15__MASK 0xff000000U #define PCU_WOW7__OFFSET15__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) #define PCU_WOW7__OFFSET15__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) #define PCU_WOW7__OFFSET15__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define PCU_WOW7__OFFSET15__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define PCU_WOW7__TYPE u_int32_t #define PCU_WOW7__READ 0xffffffffU #define PCU_WOW7__WRITE 0xffffffffU #endif /* __PCU_WOW7_MACRO__ */ /* macros for mac_pcu_reg_map.PCU_WOW7 */ #define INST_MAC_PCU_REG_MAP__PCU_WOW7__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH3 */ #ifndef __MAC_PCU_WOW_LENGTH3_MACRO__ #define __MAC_PCU_WOW_LENGTH3_MACRO__ /* macros for field PATTERN_11 */ #define MAC_PCU_WOW_LENGTH3__PATTERN_11__SHIFT 0 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__WIDTH 8 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__MASK 0x000000ffU #define MAC_PCU_WOW_LENGTH3__PATTERN_11__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_WOW_LENGTH3__PATTERN_11__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_WOW_LENGTH3__PATTERN_11__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field PATTERN_10 */ #define MAC_PCU_WOW_LENGTH3__PATTERN_10__SHIFT 8 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__WIDTH 8 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__MASK 0x0000ff00U #define MAC_PCU_WOW_LENGTH3__PATTERN_10__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_WOW_LENGTH3__PATTERN_10__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH3__PATTERN_10__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field PATTERN_9 */ #define MAC_PCU_WOW_LENGTH3__PATTERN_9__SHIFT 16 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__WIDTH 8 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__MASK 0x00ff0000U #define MAC_PCU_WOW_LENGTH3__PATTERN_9__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_WOW_LENGTH3__PATTERN_9__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH3__PATTERN_9__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field PATTERN_8 */ #define MAC_PCU_WOW_LENGTH3__PATTERN_8__SHIFT 24 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__WIDTH 8 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__MASK 0xff000000U #define MAC_PCU_WOW_LENGTH3__PATTERN_8__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_WOW_LENGTH3__PATTERN_8__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH3__PATTERN_8__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_WOW_LENGTH3__TYPE u_int32_t #define MAC_PCU_WOW_LENGTH3__READ 0xffffffffU #define MAC_PCU_WOW_LENGTH3__WRITE 0xffffffffU #endif /* __MAC_PCU_WOW_LENGTH3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH4 */ #ifndef __MAC_PCU_WOW_LENGTH4_MACRO__ #define __MAC_PCU_WOW_LENGTH4_MACRO__ /* macros for field PATTERN_15 */ #define MAC_PCU_WOW_LENGTH4__PATTERN_15__SHIFT 0 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__WIDTH 8 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__MASK 0x000000ffU #define MAC_PCU_WOW_LENGTH4__PATTERN_15__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_WOW_LENGTH4__PATTERN_15__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_WOW_LENGTH4__PATTERN_15__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field PATTERN_14 */ #define MAC_PCU_WOW_LENGTH4__PATTERN_14__SHIFT 8 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__WIDTH 8 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__MASK 0x0000ff00U #define MAC_PCU_WOW_LENGTH4__PATTERN_14__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_WOW_LENGTH4__PATTERN_14__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_WOW_LENGTH4__PATTERN_14__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field PATTERN_13 */ #define MAC_PCU_WOW_LENGTH4__PATTERN_13__SHIFT 16 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__WIDTH 8 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__MASK 0x00ff0000U #define MAC_PCU_WOW_LENGTH4__PATTERN_13__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_WOW_LENGTH4__PATTERN_13__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_WOW_LENGTH4__PATTERN_13__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field PATTERN_12 */ #define MAC_PCU_WOW_LENGTH4__PATTERN_12__SHIFT 24 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__WIDTH 8 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__MASK 0xff000000U #define MAC_PCU_WOW_LENGTH4__PATTERN_12__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_WOW_LENGTH4__PATTERN_12__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_WOW_LENGTH4__PATTERN_12__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_WOW_LENGTH4__TYPE u_int32_t #define MAC_PCU_WOW_LENGTH4__READ 0xffffffffU #define MAC_PCU_WOW_LENGTH4__WRITE 0xffffffffU #endif /* __MAC_PCU_WOW_LENGTH4_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH4 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH4__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_CONTROL */ #ifndef __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ #define __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ /* macros for field ENABLE */ #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SHIFT 0 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WIDTH 1 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MASK 0x00000001U #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field UPLOAD_H_DISABLE */ #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SHIFT 1 #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WIDTH 1 #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MASK 0x00000002U #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) #define MAC_PCU_LOCATION_MODE_CONTROL__TYPE u_int32_t #define MAC_PCU_LOCATION_MODE_CONTROL__READ 0x00000003U #define MAC_PCU_LOCATION_MODE_CONTROL__WRITE 0x00000003U #endif /* __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_CONTROL */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_CONTROL__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_TIMER */ #ifndef __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ #define __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ /* macros for field VALUE */ #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__SHIFT 0 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WIDTH 32 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MASK 0xffffffffU #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_LOCATION_MODE_TIMER__TYPE u_int32_t #define MAC_PCU_LOCATION_MODE_TIMER__READ 0xffffffffU #define MAC_PCU_LOCATION_MODE_TIMER__WRITE 0xffffffffU #endif /* __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_TIMER */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_TIMER__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_L32 */ #ifndef __MAC_PCU_TSF2_L32_MACRO__ #define __MAC_PCU_TSF2_L32_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TSF2_L32__VALUE__SHIFT 0 #define MAC_PCU_TSF2_L32__VALUE__WIDTH 32 #define MAC_PCU_TSF2_L32__VALUE__MASK 0xffffffffU #define MAC_PCU_TSF2_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TSF2_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TSF2_L32__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TSF2_L32__TYPE u_int32_t #define MAC_PCU_TSF2_L32__READ 0xffffffffU #define MAC_PCU_TSF2_L32__WRITE 0xffffffffU #endif /* __MAC_PCU_TSF2_L32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TSF2_L32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_L32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_U32 */ #ifndef __MAC_PCU_TSF2_U32_MACRO__ #define __MAC_PCU_TSF2_U32_MACRO__ /* macros for field VALUE */ #define MAC_PCU_TSF2_U32__VALUE__SHIFT 0 #define MAC_PCU_TSF2_U32__VALUE__WIDTH 32 #define MAC_PCU_TSF2_U32__VALUE__MASK 0xffffffffU #define MAC_PCU_TSF2_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TSF2_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TSF2_U32__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TSF2_U32__TYPE u_int32_t #define MAC_PCU_TSF2_U32__READ 0xffffffffU #define MAC_PCU_TSF2_U32__WRITE 0xffffffffU #endif /* __MAC_PCU_TSF2_U32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TSF2_U32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_U32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_L32 */ #ifndef __MAC_PCU_BSSID2_L32_MACRO__ #define __MAC_PCU_BSSID2_L32_MACRO__ /* macros for field ADDR */ #define MAC_PCU_BSSID2_L32__ADDR__SHIFT 0 #define MAC_PCU_BSSID2_L32__ADDR__WIDTH 32 #define MAC_PCU_BSSID2_L32__ADDR__MASK 0xffffffffU #define MAC_PCU_BSSID2_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_BSSID2_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BSSID2_L32__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BSSID2_L32__TYPE u_int32_t #define MAC_PCU_BSSID2_L32__READ 0xffffffffU #define MAC_PCU_BSSID2_L32__WRITE 0xffffffffU #endif /* __MAC_PCU_BSSID2_L32_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_L32 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_L32__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_U16 */ #ifndef __MAC_PCU_BSSID2_U16_MACRO__ #define __MAC_PCU_BSSID2_U16_MACRO__ /* macros for field ADDR */ #define MAC_PCU_BSSID2_U16__ADDR__SHIFT 0 #define MAC_PCU_BSSID2_U16__ADDR__WIDTH 16 #define MAC_PCU_BSSID2_U16__ADDR__MASK 0x0000ffffU #define MAC_PCU_BSSID2_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU #define MAC_PCU_BSSID2_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) #define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ffffU) | ((u_int32_t)(src) &\ 0x0000ffffU) #define MAC_PCU_BSSID2_U16__ADDR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000ffffU))) /* macros for field ENABLE */ #define MAC_PCU_BSSID2_U16__ENABLE__SHIFT 16 #define MAC_PCU_BSSID2_U16__ENABLE__WIDTH 1 #define MAC_PCU_BSSID2_U16__ENABLE__MASK 0x00010000U #define MAC_PCU_BSSID2_U16__ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_BSSID2_U16__ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_BSSID2_U16__ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_BSSID2_U16__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_BSSID2_U16__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) #define MAC_PCU_BSSID2_U16__TYPE u_int32_t #define MAC_PCU_BSSID2_U16__READ 0x0001ffffU #define MAC_PCU_BSSID2_U16__WRITE 0x0001ffffU #endif /* __MAC_PCU_BSSID2_U16_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_U16 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_U16__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_DIRECT_CONNECT */ #ifndef __MAC_PCU_DIRECT_CONNECT_MACRO__ #define __MAC_PCU_DIRECT_CONNECT_MACRO__ /* macros for field AP_STA_ENABLE */ #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SHIFT 0 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MASK 0x00000001U #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field TBTT_TIMER_0_8_SEL */ #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SHIFT 4 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MASK 0x00000010U #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field DMA_BALERT_TIMER_1_9_SEL */ #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SHIFT 5 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MASK 0x00000020U #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field SW_BALERT_TIMER_2_10_SEL */ #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SHIFT 6 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MASK 0x00000040U #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field HCF_TO_TIMER_3_11_SEL */ #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SHIFT 7 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MASK 0x00000080U #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field NEXT_TIM_TIMER_4_12_SEL */ #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SHIFT 8 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MASK 0x00000100U #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field NEXT_DTIM_TIMER_5_13_SEL */ #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SHIFT 9 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MASK 0x00000200U #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field QUIET_TM_TIMER_6_14_SEL */ #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SHIFT 10 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MASK 0x00000400U #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field TBTT2_TIMER_0_8_SEL */ #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SHIFT 11 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MASK 0x00000800U #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field AP_TSF_1_2_SEL */ #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SHIFT 12 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MASK 0x00001000U #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field STA_TSF_1_2_SEL */ #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SHIFT 13 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MASK 0x00002000U #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00002000U) >> 13) #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 13) & 0x00002000U) #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00002000U) | (((u_int32_t)(src) <<\ 13) & 0x00002000U) #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 13) & ~0x00002000U))) #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(1) << 13) #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(0) << 13) /* macros for field BC_MC_WAPI_MODE2_EN */ #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SHIFT 14 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MASK 0x00004000U #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00004000U) >> 14) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x00004000U) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00004000U) | (((u_int32_t)(src) <<\ 14) & 0x00004000U) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x00004000U))) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(1) << 14) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(0) << 14) /* macros for field BC_MC_WAPI_MODE_AP_SEL */ #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SHIFT 15 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MASK 0x00008000U #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__READ(src) \ (((u_int32_t)(src)\ & 0x00008000U) >> 15) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WRITE(src) \ (((u_int32_t)(src)\ << 15) & 0x00008000U) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00008000U) | (((u_int32_t)(src) <<\ 15) & 0x00008000U) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 15) & ~0x00008000U))) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SET(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(1) << 15) #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__CLR(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(0) << 15) /* macros for field DESC_SVD_TSF_SEL_EN */ #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SHIFT 16 #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WIDTH 1 #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MASK 0x00010000U #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) #define MAC_PCU_DIRECT_CONNECT__TYPE u_int32_t #define MAC_PCU_DIRECT_CONNECT__READ 0x0001fff1U #define MAC_PCU_DIRECT_CONNECT__WRITE 0x0001fff1U #endif /* __MAC_PCU_DIRECT_CONNECT_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_DIRECT_CONNECT */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_DIRECT_CONNECT__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TID_TO_AC */ #ifndef __MAC_PCU_TID_TO_AC_MACRO__ #define __MAC_PCU_TID_TO_AC_MACRO__ /* macros for field DATA */ #define MAC_PCU_TID_TO_AC__DATA__SHIFT 0 #define MAC_PCU_TID_TO_AC__DATA__WIDTH 32 #define MAC_PCU_TID_TO_AC__DATA__MASK 0xffffffffU #define MAC_PCU_TID_TO_AC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TID_TO_AC__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TID_TO_AC__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TID_TO_AC__TYPE u_int32_t #define MAC_PCU_TID_TO_AC__READ 0xffffffffU #define MAC_PCU_TID_TO_AC__WRITE 0xffffffffU #endif /* __MAC_PCU_TID_TO_AC_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TID_TO_AC */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TID_TO_AC__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_HP_QUEUE */ #ifndef __MAC_PCU_HP_QUEUE_MACRO__ #define __MAC_PCU_HP_QUEUE_MACRO__ /* macros for field ENABLE */ #define MAC_PCU_HP_QUEUE__ENABLE__SHIFT 0 #define MAC_PCU_HP_QUEUE__ENABLE__WIDTH 1 #define MAC_PCU_HP_QUEUE__ENABLE__MASK 0x00000001U #define MAC_PCU_HP_QUEUE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_HP_QUEUE__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_HP_QUEUE__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_HP_QUEUE__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_HP_QUEUE__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field AC_MASK_BE */ #define MAC_PCU_HP_QUEUE__AC_MASK_BE__SHIFT 1 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__WIDTH 1 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__MASK 0x00000002U #define MAC_PCU_HP_QUEUE__AC_MASK_BE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_HP_QUEUE__AC_MASK_BE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_HP_QUEUE__AC_MASK_BE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_HP_QUEUE__AC_MASK_BE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_HP_QUEUE__AC_MASK_BE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field AC_MASK_BK */ #define MAC_PCU_HP_QUEUE__AC_MASK_BK__SHIFT 2 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__WIDTH 1 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__MASK 0x00000004U #define MAC_PCU_HP_QUEUE__AC_MASK_BK__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_HP_QUEUE__AC_MASK_BK__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_HP_QUEUE__AC_MASK_BK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_HP_QUEUE__AC_MASK_BK__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_HP_QUEUE__AC_MASK_BK__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field AC_MASK_VI */ #define MAC_PCU_HP_QUEUE__AC_MASK_VI__SHIFT 3 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__WIDTH 1 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__MASK 0x00000008U #define MAC_PCU_HP_QUEUE__AC_MASK_VI__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_HP_QUEUE__AC_MASK_VI__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_HP_QUEUE__AC_MASK_VI__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_HP_QUEUE__AC_MASK_VI__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_HP_QUEUE__AC_MASK_VI__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field AC_MASK_VO */ #define MAC_PCU_HP_QUEUE__AC_MASK_VO__SHIFT 4 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__WIDTH 1 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__MASK 0x00000010U #define MAC_PCU_HP_QUEUE__AC_MASK_VO__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_HP_QUEUE__AC_MASK_VO__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_HP_QUEUE__AC_MASK_VO__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_HP_QUEUE__AC_MASK_VO__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_HP_QUEUE__AC_MASK_VO__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field HPQON_UAPSD */ #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SHIFT 5 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WIDTH 1 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MASK 0x00000020U #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field FRAME_FILTER_ENABLE0 */ #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SHIFT 6 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WIDTH 1 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MASK 0x00000040U #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field FRAME_BSSID_MATCH0 */ #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SHIFT 7 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WIDTH 1 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MASK 0x00000080U #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field FRAME_TYPE0 */ #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__SHIFT 8 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WIDTH 2 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MASK 0x00000300U #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__READ(src) \ (((u_int32_t)(src)\ & 0x00000300U) >> 8) #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000300U) #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000300U) | (((u_int32_t)(src) <<\ 8) & 0x00000300U) #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000300U))) /* macros for field FRAME_TYPE_MASK0 */ #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__SHIFT 10 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WIDTH 2 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MASK 0x00000c00U #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__READ(src) \ (((u_int32_t)(src)\ & 0x00000c00U) >> 10) #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000c00U) #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000c00U) | (((u_int32_t)(src) <<\ 10) & 0x00000c00U) #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000c00U))) /* macros for field FRAME_SUBTYPE0 */ #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__SHIFT 12 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WIDTH 4 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MASK 0x0000f000U #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__READ(src) \ (((u_int32_t)(src)\ & 0x0000f000U) >> 12) #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x0000f000U) #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000f000U) | (((u_int32_t)(src) <<\ 12) & 0x0000f000U) #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x0000f000U))) /* macros for field FRAME_SUBTYPE_MASK0 */ #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__SHIFT 16 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WIDTH 4 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MASK 0x000f0000U #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__READ(src) \ (((u_int32_t)(src)\ & 0x000f0000U) >> 16) #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x000f0000U) #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000f0000U) | (((u_int32_t)(src) <<\ 16) & 0x000f0000U) #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x000f0000U))) /* macros for field UAPSD_EN */ #define MAC_PCU_HP_QUEUE__UAPSD_EN__SHIFT 20 #define MAC_PCU_HP_QUEUE__UAPSD_EN__WIDTH 1 #define MAC_PCU_HP_QUEUE__UAPSD_EN__MASK 0x00100000U #define MAC_PCU_HP_QUEUE__UAPSD_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_HP_QUEUE__UAPSD_EN__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_HP_QUEUE__UAPSD_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_HP_QUEUE__UAPSD_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_HP_QUEUE__UAPSD_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field PM_CHANGE */ #define MAC_PCU_HP_QUEUE__PM_CHANGE__SHIFT 21 #define MAC_PCU_HP_QUEUE__PM_CHANGE__WIDTH 1 #define MAC_PCU_HP_QUEUE__PM_CHANGE__MASK 0x00200000U #define MAC_PCU_HP_QUEUE__PM_CHANGE__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_HP_QUEUE__PM_CHANGE__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_PCU_HP_QUEUE__PM_CHANGE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_PCU_HP_QUEUE__PM_CHANGE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_PCU_HP_QUEUE__PM_CHANGE__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_HP_QUEUE__PM_CHANGE__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field NON_UAPSD_EN */ #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SHIFT 22 #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WIDTH 1 #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MASK 0x00400000U #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) #define MAC_PCU_HP_QUEUE__TYPE u_int32_t #define MAC_PCU_HP_QUEUE__READ 0x007fffffU #define MAC_PCU_HP_QUEUE__WRITE 0x007fffffU #endif /* __MAC_PCU_HP_QUEUE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_HP_QUEUE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_HP_QUEUE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */ #ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ #define __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__READ 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__WRITE 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */ #ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ #define __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__READ 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__WRITE 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */ #ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ #define __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__READ 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__WRITE 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */ #ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ #define __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ /* macros for field VALUE */ #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__SHIFT 0 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WIDTH 32 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MASK 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__TYPE u_int32_t #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__READ 0xffffffffU #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__WRITE 0xffffffffU #endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT0 */ #ifndef __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ #define __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ /* macros for field VALUE */ #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__SHIFT 0 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WIDTH 32 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MASK 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_AGC_SATURATION_CNT0__TYPE u_int32_t #define MAC_PCU_AGC_SATURATION_CNT0__READ 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT0__WRITE 0xffffffffU #endif /* __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT0 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT0__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT1 */ #ifndef __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ #define __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ /* macros for field VALUE */ #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__SHIFT 0 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WIDTH 32 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MASK 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_AGC_SATURATION_CNT1__TYPE u_int32_t #define MAC_PCU_AGC_SATURATION_CNT1__READ 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT1__WRITE 0xffffffffU #endif /* __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT2 */ #ifndef __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ #define __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ /* macros for field VALUE */ #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__SHIFT 0 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WIDTH 32 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MASK 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_AGC_SATURATION_CNT2__TYPE u_int32_t #define MAC_PCU_AGC_SATURATION_CNT2__READ 0xffffffffU #define MAC_PCU_AGC_SATURATION_CNT2__WRITE 0xffffffffU #endif /* __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC1 */ #ifndef __MAC_PCU_HW_BCN_PROC1_MACRO__ #define __MAC_PCU_HW_BCN_PROC1_MACRO__ /* macros for field CRC_ENABLE */ #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SHIFT 0 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MASK 0x00000001U #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field RESET_CRC */ #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SHIFT 1 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MASK 0x00000002U #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field EXCLUDE_BCN_INTVL */ #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SHIFT 2 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MASK 0x00000004U #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field EXCLUDE_CAP_INFO */ #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SHIFT 3 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MASK 0x00000008U #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field EXCLUDE_TIM_ELM */ #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SHIFT 4 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MASK 0x00000010U #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field EXCLUDE_ELM0 */ #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SHIFT 5 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MASK 0x00000020U #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field EXCLUDE_ELM1 */ #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SHIFT 6 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MASK 0x00000040U #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field EXCLUDE_ELM2 */ #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SHIFT 7 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WIDTH 1 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MASK 0x00000080U #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field ELM0_ID */ #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__SHIFT 8 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WIDTH 8 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MASK 0x0000ff00U #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field ELM1_ID */ #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__SHIFT 16 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WIDTH 8 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MASK 0x00ff0000U #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) /* macros for field ELM2_ID */ #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__SHIFT 24 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WIDTH 8 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MASK 0xff000000U #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__READ(src) \ (((u_int32_t)(src)\ & 0xff000000U) >> 24) #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0xff000000U) #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xff000000U) | (((u_int32_t)(src) <<\ 24) & 0xff000000U) #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0xff000000U))) #define MAC_PCU_HW_BCN_PROC1__TYPE u_int32_t #define MAC_PCU_HW_BCN_PROC1__READ 0xffffffffU #define MAC_PCU_HW_BCN_PROC1__WRITE 0xffffffffU #endif /* __MAC_PCU_HW_BCN_PROC1_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC1 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC1__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC2 */ #ifndef __MAC_PCU_HW_BCN_PROC2_MACRO__ #define __MAC_PCU_HW_BCN_PROC2_MACRO__ /* macros for field FILTER_INTERVAL_ENABLE */ #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SHIFT 0 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WIDTH 1 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MASK 0x00000001U #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field RESET_INTERVAL */ #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SHIFT 1 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WIDTH 1 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MASK 0x00000002U #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field EXCLUDE_ELM3 */ #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SHIFT 2 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WIDTH 1 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MASK 0x00000004U #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field FILTER_INTERVAL */ #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__SHIFT 8 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WIDTH 8 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MASK 0x0000ff00U #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field ELM3_ID */ #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__SHIFT 16 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WIDTH 8 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MASK 0x00ff0000U #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__READ(src) \ (((u_int32_t)(src)\ & 0x00ff0000U) >> 16) #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00ff0000U) #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00ff0000U) | (((u_int32_t)(src) <<\ 16) & 0x00ff0000U) #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00ff0000U))) #define MAC_PCU_HW_BCN_PROC2__TYPE u_int32_t #define MAC_PCU_HW_BCN_PROC2__READ 0x00ffff07U #define MAC_PCU_HW_BCN_PROC2__WRITE 0x00ffff07U #endif /* __MAC_PCU_HW_BCN_PROC2_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC2 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC2__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE3 */ #ifndef __MAC_PCU_MISC_MODE3_MACRO__ #define __MAC_PCU_MISC_MODE3_MACRO__ /* macros for field BUG_55702_FIX_ENABLE */ #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SHIFT 0 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MASK 0x00000001U #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field AES_3STREAM */ #define MAC_PCU_MISC_MODE3__AES_3STREAM__SHIFT 1 #define MAC_PCU_MISC_MODE3__AES_3STREAM__WIDTH 1 #define MAC_PCU_MISC_MODE3__AES_3STREAM__MASK 0x00000002U #define MAC_PCU_MISC_MODE3__AES_3STREAM__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_MISC_MODE3__AES_3STREAM__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_MISC_MODE3__AES_3STREAM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_MISC_MODE3__AES_3STREAM__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_MISC_MODE3__AES_3STREAM__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) /* macros for field REGULAR_SOUNDING */ #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SHIFT 2 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WIDTH 1 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MASK 0x00000004U #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__READ(src) \ (((u_int32_t)(src)\ & 0x00000004U) >> 2) #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WRITE(src) \ (((u_int32_t)(src)\ << 2) & 0x00000004U) #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000004U) | (((u_int32_t)(src) <<\ 2) & 0x00000004U) #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 2) & ~0x00000004U))) #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SET(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(1) << 2) #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__CLR(dst) \ (dst) = ((dst) &\ ~0x00000004U) | ((u_int32_t)(0) << 2) /* macros for field BUG_58011_FIX_ENABLE */ #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SHIFT 3 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MASK 0x00000008U #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000008U) >> 3) #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 3) & 0x00000008U) #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000008U) | (((u_int32_t)(src) <<\ 3) & 0x00000008U) #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 3) & ~0x00000008U))) #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(1) << 3) #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000008U) | ((u_int32_t)(0) << 3) /* macros for field BUG_56991_FIX_ENABLE */ #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SHIFT 4 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MASK 0x00000010U #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000010U) >> 4) #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 4) & 0x00000010U) #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000010U) | (((u_int32_t)(src) <<\ 4) & 0x00000010U) #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 4) & ~0x00000010U))) #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(1) << 4) #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000010U) | ((u_int32_t)(0) << 4) /* macros for field WOW_ADDR1_MASK_ENABLE */ #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SHIFT 5 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MASK 0x00000020U #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000020U) >> 5) #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 5) & 0x00000020U) #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000020U) | (((u_int32_t)(src) <<\ 5) & 0x00000020U) #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 5) & ~0x00000020U))) #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(1) << 5) #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000020U) | ((u_int32_t)(0) << 5) /* macros for field BUG_61936_FIX_ENABLE */ #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SHIFT 6 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MASK 0x00000040U #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000040U) >> 6) #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 6) & 0x00000040U) #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000040U) | (((u_int32_t)(src) <<\ 6) & 0x00000040U) #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 6) & ~0x00000040U))) #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(1) << 6) #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000040U) | ((u_int32_t)(0) << 6) /* macros for field CHECK_LENGTH_FOR_BA */ #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SHIFT 7 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WIDTH 1 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MASK 0x00000080U #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__READ(src) \ (((u_int32_t)(src)\ & 0x00000080U) >> 7) #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00000080U) #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000080U) | (((u_int32_t)(src) <<\ 7) & 0x00000080U) #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00000080U))) #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SET(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(1) << 7) #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__CLR(dst) \ (dst) = ((dst) &\ ~0x00000080U) | ((u_int32_t)(0) << 7) /* macros for field BA_FRAME_LENGTH */ #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__SHIFT 8 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WIDTH 8 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MASK 0x0000ff00U #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__READ(src) \ (((u_int32_t)(src)\ & 0x0000ff00U) >> 8) #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x0000ff00U) #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000ff00U) | (((u_int32_t)(src) <<\ 8) & 0x0000ff00U) #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x0000ff00U))) /* macros for field MATCH_TID_FOR_BA */ #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SHIFT 16 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WIDTH 1 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MASK 0x00010000U #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field WAPI_ORDER_MASK */ #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SHIFT 17 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WIDTH 1 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MASK 0x00020000U #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field BB_LDPC_EN */ #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SHIFT 18 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WIDTH 1 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MASK 0x00040000U #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__READ(src) \ (((u_int32_t)(src)\ & 0x00040000U) >> 18) #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x00040000U) #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00040000U) | (((u_int32_t)(src) <<\ 18) & 0x00040000U) #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x00040000U))) #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SET(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(1) << 18) #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__CLR(dst) \ (dst) = ((dst) &\ ~0x00040000U) | ((u_int32_t)(0) << 18) /* macros for field SELF_GEN_SMOOTHING */ #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SHIFT 19 #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WIDTH 1 #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MASK 0x00080000U #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__READ(src) \ (((u_int32_t)(src)\ & 0x00080000U) >> 19) #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WRITE(src) \ (((u_int32_t)(src)\ << 19) & 0x00080000U) #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00080000U) | (((u_int32_t)(src) <<\ 19) & 0x00080000U) #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 19) & ~0x00080000U))) #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SET(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(1) << 19) #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__CLR(dst) \ (dst) = ((dst) &\ ~0x00080000U) | ((u_int32_t)(0) << 19) /* macros for field SMOOTHING_FORCE */ #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SHIFT 20 #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WIDTH 1 #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MASK 0x00100000U #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__READ(src) \ (((u_int32_t)(src)\ & 0x00100000U) >> 20) #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00100000U) #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00100000U) | (((u_int32_t)(src) <<\ 20) & 0x00100000U) #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00100000U))) #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SET(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(1) << 20) #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__CLR(dst) \ (dst) = ((dst) &\ ~0x00100000U) | ((u_int32_t)(0) << 20) /* macros for field KEY_MISS_FIX */ #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SHIFT 21 #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WIDTH 1 #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MASK 0x00200000U #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__READ(src) \ (((u_int32_t)(src)\ & 0x00200000U) >> 21) #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x00200000U) #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00200000U) | (((u_int32_t)(src) <<\ 21) & 0x00200000U) #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x00200000U))) #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SET(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(1) << 21) #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__CLR(dst) \ (dst) = ((dst) &\ ~0x00200000U) | ((u_int32_t)(0) << 21) /* macros for field RESERVED1 */ #define MAC_PCU_MISC_MODE3__RESERVED1__SHIFT 22 #define MAC_PCU_MISC_MODE3__RESERVED1__WIDTH 4 #define MAC_PCU_MISC_MODE3__RESERVED1__MASK 0x03c00000U #define MAC_PCU_MISC_MODE3__RESERVED1__READ(src) \ (((u_int32_t)(src)\ & 0x03c00000U) >> 22) #define MAC_PCU_MISC_MODE3__RESERVED1__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x03c00000U) #define MAC_PCU_MISC_MODE3__RESERVED1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x03c00000U) | (((u_int32_t)(src) <<\ 22) & 0x03c00000U) #define MAC_PCU_MISC_MODE3__RESERVED1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x03c00000U))) /* macros for field PHY_ERROR_AIFS_MASK_ENABLE */ #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SHIFT 26 #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MASK 0x04000000U #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x04000000U) >> 26) #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 26) & 0x04000000U) #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x04000000U) | (((u_int32_t)(src) <<\ 26) & 0x04000000U) #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 26) & ~0x04000000U))) #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(1) << 26) #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x04000000U) | ((u_int32_t)(0) << 26) /* macros for field RESERVED */ #define MAC_PCU_MISC_MODE3__RESERVED__SHIFT 27 #define MAC_PCU_MISC_MODE3__RESERVED__WIDTH 3 #define MAC_PCU_MISC_MODE3__RESERVED__MASK 0x38000000U #define MAC_PCU_MISC_MODE3__RESERVED__READ(src) \ (((u_int32_t)(src)\ & 0x38000000U) >> 27) #define MAC_PCU_MISC_MODE3__RESERVED__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x38000000U) #define MAC_PCU_MISC_MODE3__RESERVED__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x38000000U) | (((u_int32_t)(src) <<\ 27) & 0x38000000U) #define MAC_PCU_MISC_MODE3__RESERVED__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x38000000U))) /* macros for field PER_STA_WEP_ENTRY_ENABLE */ #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SHIFT 30 #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WIDTH 1 #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MASK 0x40000000U #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) /* macros for field BC_MC_WAPI_MODE2 */ #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SHIFT 31 #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WIDTH 1 #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MASK 0x80000000U #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define MAC_PCU_MISC_MODE3__TYPE u_int32_t #define MAC_PCU_MISC_MODE3__READ 0xffffffffU #define MAC_PCU_MISC_MODE3__WRITE 0xffffffffU #endif /* __MAC_PCU_MISC_MODE3_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE3 */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE3__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_RSSI_AVE */ #ifndef __MAC_PCU_FILTER_RSSI_AVE_MACRO__ #define __MAC_PCU_FILTER_RSSI_AVE_MACRO__ /* macros for field AVE_VALUE */ #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__SHIFT 0 #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WIDTH 8 #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MASK 0x000000ffU #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field NUM_FRAMES_EXPONENT */ #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__SHIFT 8 #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WIDTH 3 #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MASK 0x00000700U #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__READ(src) \ (((u_int32_t)(src)\ & 0x00000700U) >> 8) #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000700U) #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000700U) | (((u_int32_t)(src) <<\ 8) & 0x00000700U) #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000700U))) /* macros for field ENABLE */ #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SHIFT 11 #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WIDTH 1 #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MASK 0x00000800U #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field RESET */ #define MAC_PCU_FILTER_RSSI_AVE__RESET__SHIFT 12 #define MAC_PCU_FILTER_RSSI_AVE__RESET__WIDTH 1 #define MAC_PCU_FILTER_RSSI_AVE__RESET__MASK 0x00001000U #define MAC_PCU_FILTER_RSSI_AVE__RESET__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define MAC_PCU_FILTER_RSSI_AVE__RESET__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define MAC_PCU_FILTER_RSSI_AVE__RESET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define MAC_PCU_FILTER_RSSI_AVE__RESET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define MAC_PCU_FILTER_RSSI_AVE__RESET__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define MAC_PCU_FILTER_RSSI_AVE__RESET__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) #define MAC_PCU_FILTER_RSSI_AVE__TYPE u_int32_t #define MAC_PCU_FILTER_RSSI_AVE__READ 0x00001fffU #define MAC_PCU_FILTER_RSSI_AVE__WRITE 0x00001fffU #endif /* __MAC_PCU_FILTER_RSSI_AVE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_FILTER_RSSI_AVE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_RSSI_AVE__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_AIFS_MASK */ #ifndef __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ #define __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ /* macros for field VALUE */ #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__SHIFT 0 #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WIDTH 32 #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MASK 0xffffffffU #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__READ(src) \ (u_int32_t)(src)\ & 0xffffffffU #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WRITE(src) \ ((u_int32_t)(src)\ & 0xffffffffU) #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_PHY_ERROR_AIFS_MASK__TYPE u_int32_t #define MAC_PCU_PHY_ERROR_AIFS_MASK__READ 0xffffffffU #define MAC_PCU_PHY_ERROR_AIFS_MASK__WRITE 0xffffffffU #endif /* __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_AIFS_MASK */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_AIFS_MASK__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_PS_FILTER */ #ifndef __MAC_PCU_PS_FILTER_MACRO__ #define __MAC_PCU_PS_FILTER_MACRO__ /* macros for field ENABLE */ #define MAC_PCU_PS_FILTER__ENABLE__SHIFT 0 #define MAC_PCU_PS_FILTER__ENABLE__WIDTH 1 #define MAC_PCU_PS_FILTER__ENABLE__MASK 0x00000001U #define MAC_PCU_PS_FILTER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U #define MAC_PCU_PS_FILTER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) #define MAC_PCU_PS_FILTER__ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define MAC_PCU_PS_FILTER__ENABLE__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define MAC_PCU_PS_FILTER__ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define MAC_PCU_PS_FILTER__ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field PS_SAVE_ENABLE */ #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SHIFT 1 #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WIDTH 1 #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MASK 0x00000002U #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x00000002U) >> 1) #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x00000002U) #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000002U) | (((u_int32_t)(src) <<\ 1) & 0x00000002U) #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x00000002U))) #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(1) << 1) #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000002U) | ((u_int32_t)(0) << 1) #define MAC_PCU_PS_FILTER__TYPE u_int32_t #define MAC_PCU_PS_FILTER__READ 0x00000003U #define MAC_PCU_PS_FILTER__WRITE 0x00000003U #endif /* __MAC_PCU_PS_FILTER_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_PS_FILTER */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_PS_FILTER__NUM 1 /* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_BA */ #ifndef __MAC_PCU_TXBUF_BA_MACRO__ #define __MAC_PCU_TXBUF_BA_MACRO__ /* macros for field DATA */ #define MAC_PCU_TXBUF_BA__DATA__SHIFT 0 #define MAC_PCU_TXBUF_BA__DATA__WIDTH 32 #define MAC_PCU_TXBUF_BA__DATA__MASK 0xffffffffU #define MAC_PCU_TXBUF_BA__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_TXBUF_BA__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_TXBUF_BA__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_TXBUF_BA__TYPE u_int32_t #define MAC_PCU_TXBUF_BA__READ 0xffffffffU #define MAC_PCU_TXBUF_BA__WRITE 0xffffffffU #endif /* __MAC_PCU_TXBUF_BA_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_BA */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_BA__NUM 64 /* macros for BlueprintGlobalNameSpace::MAC_PCU_KEY_CACHE */ #ifndef __MAC_PCU_KEY_CACHE_MACRO__ #define __MAC_PCU_KEY_CACHE_MACRO__ /* macros for field DATA */ #define MAC_PCU_KEY_CACHE__DATA__SHIFT 0 #define MAC_PCU_KEY_CACHE__DATA__WIDTH 32 #define MAC_PCU_KEY_CACHE__DATA__MASK 0xffffffffU #define MAC_PCU_KEY_CACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU #define MAC_PCU_KEY_CACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) #define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xffffffffU) | ((u_int32_t)(src) &\ 0xffffffffU) #define MAC_PCU_KEY_CACHE__DATA__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0xffffffffU))) #define MAC_PCU_KEY_CACHE__TYPE u_int32_t #define MAC_PCU_KEY_CACHE__READ 0xffffffffU #define MAC_PCU_KEY_CACHE__WRITE 0xffffffffU #endif /* __MAC_PCU_KEY_CACHE_MACRO__ */ /* macros for mac_pcu_reg_map.MAC_PCU_KEY_CACHE */ #define INST_MAC_PCU_REG_MAP__MAC_PCU_KEY_CACHE__NUM 1024 /* macros for BlueprintGlobalNameSpace::timing_controls_1 */ #ifndef __TIMING_CONTROLS_1_MACRO__ #define __TIMING_CONTROLS_1_MACRO__ /* macros for field ste_thr */ #define TIMING_CONTROLS_1__STE_THR__SHIFT 0 #define TIMING_CONTROLS_1__STE_THR__WIDTH 7 #define TIMING_CONTROLS_1__STE_THR__MASK 0x0000007fU #define TIMING_CONTROLS_1__STE_THR__READ(src) (u_int32_t)(src) & 0x0000007fU #define TIMING_CONTROLS_1__STE_THR__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) #define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000007fU) | ((u_int32_t)(src) &\ 0x0000007fU) #define TIMING_CONTROLS_1__STE_THR__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x0000007fU))) /* macros for field ste_to_long1 */ #define TIMING_CONTROLS_1__STE_TO_LONG1__SHIFT 7 #define TIMING_CONTROLS_1__STE_TO_LONG1__WIDTH 6 #define TIMING_CONTROLS_1__STE_TO_LONG1__MASK 0x00001f80U #define TIMING_CONTROLS_1__STE_TO_LONG1__READ(src) \ (((u_int32_t)(src)\ & 0x00001f80U) >> 7) #define TIMING_CONTROLS_1__STE_TO_LONG1__WRITE(src) \ (((u_int32_t)(src)\ << 7) & 0x00001f80U) #define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001f80U) | (((u_int32_t)(src) <<\ 7) & 0x00001f80U) #define TIMING_CONTROLS_1__STE_TO_LONG1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 7) & ~0x00001f80U))) /* macros for field timing_backoff */ #define TIMING_CONTROLS_1__TIMING_BACKOFF__SHIFT 13 #define TIMING_CONTROLS_1__TIMING_BACKOFF__WIDTH 4 #define TIMING_CONTROLS_1__TIMING_BACKOFF__MASK 0x0001e000U #define TIMING_CONTROLS_1__TIMING_BACKOFF__READ(src) \ (((u_int32_t)(src)\ & 0x0001e000U) >> 13) #define TIMING_CONTROLS_1__TIMING_BACKOFF__WRITE(src) \ (((u_int32_t)(src)\ << 13) & 0x0001e000U) #define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0001e000U) | (((u_int32_t)(src) <<\ 13) & 0x0001e000U) #define TIMING_CONTROLS_1__TIMING_BACKOFF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 13) & ~0x0001e000U))) /* macros for field enable_ht_fine_ppm */ #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SHIFT 17 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WIDTH 1 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MASK 0x00020000U #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__READ(src) \ (((u_int32_t)(src)\ & 0x00020000U) >> 17) #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x00020000U) #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00020000U) | (((u_int32_t)(src) <<\ 17) & 0x00020000U) #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x00020000U))) #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SET(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(1) << 17) #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__CLR(dst) \ (dst) = ((dst) &\ ~0x00020000U) | ((u_int32_t)(0) << 17) /* macros for field ht_fine_ppm_stream */ #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__SHIFT 18 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WIDTH 2 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MASK 0x000c0000U #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__READ(src) \ (((u_int32_t)(src)\ & 0x000c0000U) >> 18) #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WRITE(src) \ (((u_int32_t)(src)\ << 18) & 0x000c0000U) #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000c0000U) | (((u_int32_t)(src) <<\ 18) & 0x000c0000U) #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 18) & ~0x000c0000U))) /* macros for field ht_fine_ppm_qam */ #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__SHIFT 20 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WIDTH 2 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MASK 0x00300000U #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__READ(src) \ (((u_int32_t)(src)\ & 0x00300000U) >> 20) #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WRITE(src) \ (((u_int32_t)(src)\ << 20) & 0x00300000U) #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00300000U) | (((u_int32_t)(src) <<\ 20) & 0x00300000U) #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 20) & ~0x00300000U))) /* macros for field enable_long_chanfil */ #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SHIFT 22 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WIDTH 1 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MASK 0x00400000U #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__READ(src) \ (((u_int32_t)(src)\ & 0x00400000U) >> 22) #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WRITE(src) \ (((u_int32_t)(src)\ << 22) & 0x00400000U) #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00400000U) | (((u_int32_t)(src) <<\ 22) & 0x00400000U) #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 22) & ~0x00400000U))) #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SET(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(1) << 22) #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__CLR(dst) \ (dst) = ((dst) &\ ~0x00400000U) | ((u_int32_t)(0) << 22) /* macros for field enable_rx_stbc */ #define TIMING_CONTROLS_1__ENABLE_RX_STBC__SHIFT 23 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__WIDTH 1 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__MASK 0x00800000U #define TIMING_CONTROLS_1__ENABLE_RX_STBC__READ(src) \ (((u_int32_t)(src)\ & 0x00800000U) >> 23) #define TIMING_CONTROLS_1__ENABLE_RX_STBC__WRITE(src) \ (((u_int32_t)(src)\ << 23) & 0x00800000U) #define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00800000U) | (((u_int32_t)(src) <<\ 23) & 0x00800000U) #define TIMING_CONTROLS_1__ENABLE_RX_STBC__VERIFY(src) \ (!((((u_int32_t)(src)\ << 23) & ~0x00800000U))) #define TIMING_CONTROLS_1__ENABLE_RX_STBC__SET(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(1) << 23) #define TIMING_CONTROLS_1__ENABLE_RX_STBC__CLR(dst) \ (dst) = ((dst) &\ ~0x00800000U) | ((u_int32_t)(0) << 23) /* macros for field enable_channel_filter */ #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SHIFT 24 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WIDTH 1 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MASK 0x01000000U #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__READ(src) \ (((u_int32_t)(src)\ & 0x01000000U) >> 24) #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x01000000U) #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x01000000U) | (((u_int32_t)(src) <<\ 24) & 0x01000000U) #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x01000000U))) #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SET(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(1) << 24) #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__CLR(dst) \ (dst) = ((dst) &\ ~0x01000000U) | ((u_int32_t)(0) << 24) /* macros for field false_alarm */ #define TIMING_CONTROLS_1__FALSE_ALARM__SHIFT 25 #define TIMING_CONTROLS_1__FALSE_ALARM__WIDTH 2 #define TIMING_CONTROLS_1__FALSE_ALARM__MASK 0x06000000U #define TIMING_CONTROLS_1__FALSE_ALARM__READ(src) \ (((u_int32_t)(src)\ & 0x06000000U) >> 25) #define TIMING_CONTROLS_1__FALSE_ALARM__WRITE(src) \ (((u_int32_t)(src)\ << 25) & 0x06000000U) #define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x06000000U) | (((u_int32_t)(src) <<\ 25) & 0x06000000U) #define TIMING_CONTROLS_1__FALSE_ALARM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 25) & ~0x06000000U))) /* macros for field enable_long_rescale */ #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SHIFT 27 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WIDTH 1 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MASK 0x08000000U #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field timing_leak_enable */ #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SHIFT 28 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WIDTH 1 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MASK 0x10000000U #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field coarse_ppm_select */ #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__SHIFT 29 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WIDTH 2 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MASK 0x60000000U #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__READ(src) \ (((u_int32_t)(src)\ & 0x60000000U) >> 29) #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x60000000U) #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x60000000U) | (((u_int32_t)(src) <<\ 29) & 0x60000000U) #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x60000000U))) /* macros for field fft_scaling */ #define TIMING_CONTROLS_1__FFT_SCALING__SHIFT 31 #define TIMING_CONTROLS_1__FFT_SCALING__WIDTH 1 #define TIMING_CONTROLS_1__FFT_SCALING__MASK 0x80000000U #define TIMING_CONTROLS_1__FFT_SCALING__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define TIMING_CONTROLS_1__FFT_SCALING__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define TIMING_CONTROLS_1__FFT_SCALING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define TIMING_CONTROLS_1__FFT_SCALING__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define TIMING_CONTROLS_1__FFT_SCALING__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define TIMING_CONTROLS_1__TYPE u_int32_t #define TIMING_CONTROLS_1__READ 0xffffffffU #define TIMING_CONTROLS_1__WRITE 0xffffffffU #endif /* __TIMING_CONTROLS_1_MACRO__ */ /* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_1 */ #define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_1__NUM 1 /* macros for BlueprintGlobalNameSpace::timing_controls_2 */ #ifndef __TIMING_CONTROLS_2_MACRO__ #define __TIMING_CONTROLS_2_MACRO__ /* macros for field forced_delta_phi_symbol */ #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__SHIFT 0 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WIDTH 12 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MASK 0x00000fffU #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__READ(src) \ (u_int32_t)(src)\ & 0x00000fffU #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000fffU) #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000fffU) | ((u_int32_t)(src) &\ 0x00000fffU) #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000fffU))) /* macros for field force_delta_phi_symbol */ #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SHIFT 12 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WIDTH 1 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MASK 0x00001000U #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field enable_magnitude_track */ #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SHIFT 13 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WIDTH 1 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MASK 0x00002000U #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__READ(src) \ (((u_int32_t)(src)\ & 0x00002000U) >> 13) #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WRITE(src) \ (((u_int32_t)(src)\ << 13) & 0x00002000U) #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00002000U) | (((u_int32_t)(src) <<\ 13) & 0x00002000U) #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 13) & ~0x00002000U))) #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SET(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(1) << 13) #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__CLR(dst) \ (dst) = ((dst) &\ ~0x00002000U) | ((u_int32_t)(0) << 13) /* macros for field enable_slope_filter */ #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SHIFT 14 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WIDTH 1 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MASK 0x00004000U #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__READ(src) \ (((u_int32_t)(src)\ & 0x00004000U) >> 14) #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WRITE(src) \ (((u_int32_t)(src)\ << 14) & 0x00004000U) #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00004000U) | (((u_int32_t)(src) <<\ 14) & 0x00004000U) #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__VERIFY(src) \ (!((((u_int32_t)(src)\ << 14) & ~0x00004000U))) #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SET(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(1) << 14) #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__CLR(dst) \ (dst) = ((dst) &\ ~0x00004000U) | ((u_int32_t)(0) << 14) /* macros for field enable_offset_filter */ #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SHIFT 15 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WIDTH 1 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MASK 0x00008000U #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__READ(src) \ (((u_int32_t)(src)\ & 0x00008000U) >> 15) #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WRITE(src) \ (((u_int32_t)(src)\ << 15) & 0x00008000U) #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00008000U) | (((u_int32_t)(src) <<\ 15) & 0x00008000U) #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__VERIFY(src) \ (!((((u_int32_t)(src)\ << 15) & ~0x00008000U))) #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SET(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(1) << 15) #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__CLR(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(0) << 15) /* macros for field dc_off_deltaf_thres */ #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__SHIFT 16 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WIDTH 7 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MASK 0x007f0000U #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__READ(src) \ (((u_int32_t)(src)\ & 0x007f0000U) >> 16) #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x007f0000U) #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x007f0000U) | (((u_int32_t)(src) <<\ 16) & 0x007f0000U) #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x007f0000U))) /* macros for field dc_off_tim_const */ #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__SHIFT 24 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WIDTH 3 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MASK 0x07000000U #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__READ(src) \ (((u_int32_t)(src)\ & 0x07000000U) >> 24) #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WRITE(src) \ (((u_int32_t)(src)\ << 24) & 0x07000000U) #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x07000000U) | (((u_int32_t)(src) <<\ 24) & 0x07000000U) #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 24) & ~0x07000000U))) /* macros for field enable_dc_offset */ #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SHIFT 27 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WIDTH 1 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MASK 0x08000000U #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__READ(src) \ (((u_int32_t)(src)\ & 0x08000000U) >> 27) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WRITE(src) \ (((u_int32_t)(src)\ << 27) & 0x08000000U) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x08000000U) | (((u_int32_t)(src) <<\ 27) & 0x08000000U) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__VERIFY(src) \ (!((((u_int32_t)(src)\ << 27) & ~0x08000000U))) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SET(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(1) << 27) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__CLR(dst) \ (dst) = ((dst) &\ ~0x08000000U) | ((u_int32_t)(0) << 27) /* macros for field enable_dc_offset_track */ #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SHIFT 28 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WIDTH 1 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MASK 0x10000000U #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field enable_weighting */ #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SHIFT 29 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WIDTH 1 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MASK 0x20000000U #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field traceback128 */ #define TIMING_CONTROLS_2__TRACEBACK128__SHIFT 30 #define TIMING_CONTROLS_2__TRACEBACK128__WIDTH 1 #define TIMING_CONTROLS_2__TRACEBACK128__MASK 0x40000000U #define TIMING_CONTROLS_2__TRACEBACK128__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define TIMING_CONTROLS_2__TRACEBACK128__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define TIMING_CONTROLS_2__TRACEBACK128__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define TIMING_CONTROLS_2__TRACEBACK128__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define TIMING_CONTROLS_2__TRACEBACK128__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) /* macros for field enable_ht_fine_timing */ #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SHIFT 31 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WIDTH 1 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MASK 0x80000000U #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define TIMING_CONTROLS_2__TYPE u_int32_t #define TIMING_CONTROLS_2__READ 0xff7fffffU #define TIMING_CONTROLS_2__WRITE 0xff7fffffU #endif /* __TIMING_CONTROLS_2_MACRO__ */ /* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_2 */ #define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_2__NUM 1 /* macros for BlueprintGlobalNameSpace::timing_controls_3 */ #ifndef __TIMING_CONTROLS_3_MACRO__ #define __TIMING_CONTROLS_3_MACRO__ /* macros for field ppm_rescue_interval */ #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__SHIFT 0 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WIDTH 8 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MASK 0x000000ffU #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__READ(src) \ (u_int32_t)(src)\ & 0x000000ffU #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WRITE(src) \ ((u_int32_t)(src)\ & 0x000000ffU) #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000ffU) | ((u_int32_t)(src) &\ 0x000000ffU) #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x000000ffU))) /* macros for field enable_ppm_rescue */ #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SHIFT 8 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WIDTH 1 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MASK 0x00000100U #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__READ(src) \ (((u_int32_t)(src)\ & 0x00000100U) >> 8) #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WRITE(src) \ (((u_int32_t)(src)\ << 8) & 0x00000100U) #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000100U) | (((u_int32_t)(src) <<\ 8) & 0x00000100U) #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 8) & ~0x00000100U))) #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SET(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(1) << 8) #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000100U) | ((u_int32_t)(0) << 8) /* macros for field enable_fine_ppm */ #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SHIFT 9 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WIDTH 1 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MASK 0x00000200U #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__READ(src) \ (((u_int32_t)(src)\ & 0x00000200U) >> 9) #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WRITE(src) \ (((u_int32_t)(src)\ << 9) & 0x00000200U) #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000200U) | (((u_int32_t)(src) <<\ 9) & 0x00000200U) #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__VERIFY(src) \ (!((((u_int32_t)(src)\ << 9) & ~0x00000200U))) #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SET(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(1) << 9) #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__CLR(dst) \ (dst) = ((dst) &\ ~0x00000200U) | ((u_int32_t)(0) << 9) /* macros for field enable_fine_interp */ #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SHIFT 10 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WIDTH 1 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MASK 0x00000400U #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__READ(src) \ (((u_int32_t)(src)\ & 0x00000400U) >> 10) #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WRITE(src) \ (((u_int32_t)(src)\ << 10) & 0x00000400U) #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000400U) | (((u_int32_t)(src) <<\ 10) & 0x00000400U) #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 10) & ~0x00000400U))) #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SET(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(1) << 10) #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__CLR(dst) \ (dst) = ((dst) &\ ~0x00000400U) | ((u_int32_t)(0) << 10) /* macros for field continuous_ppm_rescue */ #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SHIFT 11 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WIDTH 1 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MASK 0x00000800U #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__READ(src) \ (((u_int32_t)(src)\ & 0x00000800U) >> 11) #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WRITE(src) \ (((u_int32_t)(src)\ << 11) & 0x00000800U) #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000800U) | (((u_int32_t)(src) <<\ 11) & 0x00000800U) #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__VERIFY(src) \ (!((((u_int32_t)(src)\ << 11) & ~0x00000800U))) #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SET(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(1) << 11) #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__CLR(dst) \ (dst) = ((dst) &\ ~0x00000800U) | ((u_int32_t)(0) << 11) /* macros for field enable_df_chanest */ #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SHIFT 12 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WIDTH 1 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MASK 0x00001000U #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__READ(src) \ (((u_int32_t)(src)\ & 0x00001000U) >> 12) #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x00001000U) #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00001000U) | (((u_int32_t)(src) <<\ 12) & 0x00001000U) #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x00001000U))) #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SET(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(1) << 12) #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__CLR(dst) \ (dst) = ((dst) &\ ~0x00001000U) | ((u_int32_t)(0) << 12) /* macros for field delta_slope_coef_exp */ #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__SHIFT 13 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WIDTH 4 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MASK 0x0001e000U #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__READ(src) \ (((u_int32_t)(src)\ & 0x0001e000U) >> 13) #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WRITE(src) \ (((u_int32_t)(src)\ << 13) & 0x0001e000U) #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0001e000U) | (((u_int32_t)(src) <<\ 13) & 0x0001e000U) #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__VERIFY(src) \ (!((((u_int32_t)(src)\ << 13) & ~0x0001e000U))) /* macros for field delta_slope_coef_man */ #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__SHIFT 17 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WIDTH 15 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MASK 0xfffe0000U #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__READ(src) \ (((u_int32_t)(src)\ & 0xfffe0000U) >> 17) #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0xfffe0000U) #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0xfffe0000U) | (((u_int32_t)(src) <<\ 17) & 0xfffe0000U) #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0xfffe0000U))) #define TIMING_CONTROLS_3__TYPE u_int32_t #define TIMING_CONTROLS_3__READ 0xffffffffU #define TIMING_CONTROLS_3__WRITE 0xffffffffU #endif /* __TIMING_CONTROLS_3_MACRO__ */ /* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_3 */ #define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_3__NUM 1 /* macros for BlueprintGlobalNameSpace::timing_control_4 */ #ifndef __TIMING_CONTROL_4_MACRO__ #define __TIMING_CONTROL_4_MACRO__ /* macros for field cal_lg_count_max */ #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__SHIFT 12 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WIDTH 4 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MASK 0x0000f000U #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__READ(src) \ (((u_int32_t)(src)\ & 0x0000f000U) >> 12) #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WRITE(src) \ (((u_int32_t)(src)\ << 12) & 0x0000f000U) #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0000f000U) | (((u_int32_t)(src) <<\ 12) & 0x0000f000U) #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__VERIFY(src) \ (!((((u_int32_t)(src)\ << 12) & ~0x0000f000U))) /* macros for field do_gain_dc_iq_cal */ #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SHIFT 16 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WIDTH 1 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MASK 0x00010000U #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__READ(src) \ (((u_int32_t)(src)\ & 0x00010000U) >> 16) #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WRITE(src) \ (((u_int32_t)(src)\ << 16) & 0x00010000U) #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00010000U) | (((u_int32_t)(src) <<\ 16) & 0x00010000U) #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__VERIFY(src) \ (!((((u_int32_t)(src)\ << 16) & ~0x00010000U))) #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SET(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(1) << 16) #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__CLR(dst) \ (dst) = ((dst) &\ ~0x00010000U) | ((u_int32_t)(0) << 16) /* macros for field use_pilot_track_df */ #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__SHIFT 17 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WIDTH 4 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MASK 0x001e0000U #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__READ(src) \ (((u_int32_t)(src)\ & 0x001e0000U) >> 17) #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WRITE(src) \ (((u_int32_t)(src)\ << 17) & 0x001e0000U) #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x001e0000U) | (((u_int32_t)(src) <<\ 17) & 0x001e0000U) #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__VERIFY(src) \ (!((((u_int32_t)(src)\ << 17) & ~0x001e0000U))) /* macros for field early_trigger_thr */ #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__SHIFT 21 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WIDTH 7 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MASK 0x0fe00000U #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__READ(src) \ (((u_int32_t)(src)\ & 0x0fe00000U) >> 21) #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WRITE(src) \ (((u_int32_t)(src)\ << 21) & 0x0fe00000U) #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x0fe00000U) | (((u_int32_t)(src) <<\ 21) & 0x0fe00000U) #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__VERIFY(src) \ (!((((u_int32_t)(src)\ << 21) & ~0x0fe00000U))) /* macros for field enable_pilot_mask */ #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SHIFT 28 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WIDTH 1 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MASK 0x10000000U #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__READ(src) \ (((u_int32_t)(src)\ & 0x10000000U) >> 28) #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WRITE(src) \ (((u_int32_t)(src)\ << 28) & 0x10000000U) #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x10000000U) | (((u_int32_t)(src) <<\ 28) & 0x10000000U) #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 28) & ~0x10000000U))) #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SET(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(1) << 28) #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__CLR(dst) \ (dst) = ((dst) &\ ~0x10000000U) | ((u_int32_t)(0) << 28) /* macros for field enable_chan_mask */ #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SHIFT 29 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WIDTH 1 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MASK 0x20000000U #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__READ(src) \ (((u_int32_t)(src)\ & 0x20000000U) >> 29) #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WRITE(src) \ (((u_int32_t)(src)\ << 29) & 0x20000000U) #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x20000000U) | (((u_int32_t)(src) <<\ 29) & 0x20000000U) #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__VERIFY(src) \ (!((((u_int32_t)(src)\ << 29) & ~0x20000000U))) #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SET(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(1) << 29) #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__CLR(dst) \ (dst) = ((dst) &\ ~0x20000000U) | ((u_int32_t)(0) << 29) /* macros for field enable_spur_filter */ #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SHIFT 30 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WIDTH 1 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MASK 0x40000000U #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__READ(src) \ (((u_int32_t)(src)\ & 0x40000000U) >> 30) #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WRITE(src) \ (((u_int32_t)(src)\ << 30) & 0x40000000U) #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x40000000U) | (((u_int32_t)(src) <<\ 30) & 0x40000000U) #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__VERIFY(src) \ (!((((u_int32_t)(src)\ << 30) & ~0x40000000U))) #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SET(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(1) << 30) #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__CLR(dst) \ (dst) = ((dst) &\ ~0x40000000U) | ((u_int32_t)(0) << 30) /* macros for field enable_spur_rssi */ #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SHIFT 31 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WIDTH 1 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MASK 0x80000000U #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__READ(src) \ (((u_int32_t)(src)\ & 0x80000000U) >> 31) #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WRITE(src) \ (((u_int32_t)(src)\ << 31) & 0x80000000U) #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x80000000U) | (((u_int32_t)(src) <<\ 31) & 0x80000000U) #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__VERIFY(src) \ (!((((u_int32_t)(src)\ << 31) & ~0x80000000U))) #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SET(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(1) << 31) #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__CLR(dst) \ (dst) = ((dst) &\ ~0x80000000U) | ((u_int32_t)(0) << 31) #define TIMING_CONTROL_4__TYPE u_int32_t #define TIMING_CONTROL_4__READ 0xfffff000U #define TIMING_CONTROL_4__WRITE 0xfffff000U #endif /* __TIMING_CONTROL_4_MACRO__ */ /* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_4 */ #define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_4__NUM 1 /* macros for BlueprintGlobalNameSpace::timing_control_5 */ #ifndef __TIMING_CONTROL_5_MACRO__ #define __TIMING_CONTROL_5_MACRO__ /* macros for field enable_cycpwr_thr1 */ #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SHIFT 0 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WIDTH 1 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MASK 0x00000001U #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__READ(src) \ (u_int32_t)(src)\ & 0x00000001U #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WRITE(src) \ ((u_int32_t)(src)\ & 0x00000001U) #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00000001U) | ((u_int32_t)(src) &\ 0x00000001U) #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__VERIFY(src) \ (!(((u_int32_t)(src)\ & ~0x00000001U))) #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SET(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(1) #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__CLR(dst) \ (dst) = ((dst) &\ ~0x00000001U) | (u_int32_t)(0) /* macros for field cycpwr_thr1 */ #define TIMING_CONTROL_5__CYCPWR_THR1__SHIFT 1 #define TIMING_CONTROL_5__CYCPWR_THR1__WIDTH 7 #define TIMING_CONTROL_5__CYCPWR_THR1__MASK 0x000000feU #define TIMING_CONTROL_5__CYCPWR_THR1__READ(src) \ (((u_int32_t)(src)\ & 0x000000feU) >> 1) #define TIMING_CONTROL_5__CYCPWR_THR1__WRITE(src) \ (((u_int32_t)(src)\ << 1) & 0x000000feU) #define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x000000feU) | (((u_int32_t)(src) <<\ 1) & 0x000000feU) #define TIMING_CONTROL_5__CYCPWR_THR1__VERIFY(src) \ (!((((u_int32_t)(src)\ << 1) & ~0x000000feU))) /* macros for field enable_rssi_thr1a */ #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SHIFT 15 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WIDTH 1 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MASK 0x00008000U #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__READ(src) \ (((u_int32_t)(src)\ & 0x00008000U) >> 15) #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WRITE(src) \ (((u_int32_t)(src)\ << 15) & 0x00008000U) #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \ (dst) = ((dst) &\ ~0x00008000U) | (((u_int32_t)(src) <<\ 15) & 0x00008000U) #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__VERIFY(src) \ (!((((u_int32_t)(src)\ << 15) & ~0x00008000U))) #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SET(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(1) << 15) #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__CLR(dst) \ (dst) = ((dst) &\ ~0x00008000U) | ((u_int32_t)(0) << 15) /* macros for field rssi_thr1a */ #define TIMING_CONTROL_5__RSS