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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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 },
 {
  "EventName": "l3_request_g1.t1.s3.caching",
  "EventCode": "0x01",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x08",
  "UMask": "0x80"
 },
{
  "EventName": "l3_request_g1.t2.s3.caching",
  "EventCode": "0x01",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x08",
  "UMask": "0x80"
 },
{
  "EventName": "l3_request_g1.t3.s3.caching",
  "EventCode": "0x01",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x08",
  "UMask": "0x80"
 },
{
  "EventName": "l3_request_g1.t4.s3.caching",
  "EventCode": "0x01",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x08",
  "UMask": "0x80"
 },
{
  "EventName": "l3_request_g1.t5.s3.caching",
  "EventCode": "0x01",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x08",
  "UMask": "0x80"
 },
{
  "EventName": "l3_request_g1.t6.s3.caching",
  "EventCode": "0x01",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x08",
  "UMask": "0x80"
 },
{
  "EventName": "l3_request_g1.t7.s3.caching",
  "EventCode": "0x01",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x08",
  "UMask": "0x80"
 },
 {
  "EventName": "l3fillvicreq.t0.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t1.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t2.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 { 
  "EventName": "l3fillvicreq.t3.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t4.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t5.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t6.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t7.s0.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 
 {
  "EventName": "l3fillvicreq.t0.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t1.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t2.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },
 { 
  "EventName": "l3fillvicreq.t3.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t4.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t5.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t6.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t7.s1.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x02",
  "UMask": "0x01"
 },


 {
  "EventName": "l3fillvicreq.t0.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x04",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t1.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x01",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t2.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x04",
  "UMask": "0x01"
 },
 { 
  "EventName": "l3fillvicreq.t3.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x04",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t4.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x04",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t5.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x04",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t6.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x04",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t7.s2.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x04",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t0.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t1.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t2.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 { 
  "EventName": "l3fillvicreq.t3.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t4.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t5.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t6.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t7.s3.vicblk",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x08",
  "UMask": "0x01"
 },
 {
  "EventName": "l3fillvicreq.t0.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t1.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t2.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t3.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t4.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t5.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t6.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t7.s0.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x01",
  "UMask": "0x02"
 },
 
 {
  "EventName": "l3fillvicreq.t0.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t1.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t2.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t3.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t4.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t5.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t6.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t7.s1.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x02",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t0.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t1.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t2.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t3.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t4.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t5.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t6.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t7.s2.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x04",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t0.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t1.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t2.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t3.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t4.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t5.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t6.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t7.s3.chgtox",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x08",
  "UMask": "0x02"
 },
 {
  "EventName": "l3fillvicreq.t0.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t1.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t2.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t3.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t4.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t5.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t6.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t7.s0.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x01",
  "UMask": "0x04"
 },
 
 {
  "EventName": "l3fillvicreq.t0.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t1.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t2.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t3.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t4.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t5.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t6.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t7.s1.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x02",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t0.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t1.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t2.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t3.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t4.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t5.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t6.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t7.s2.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x04",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t0.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t1.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t2.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t3.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t4.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t5.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t6.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t7.s3.rdblkc_s_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x08",
  "UMask": "0x04"
 },
 {
  "EventName": "l3fillvicreq.t0.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t1.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t2.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t3.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t4.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t5.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t6.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t7.s0.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x01",
  "UMask": "0x08"
 },
 
 {
  "EventName": "l3fillvicreq.t0.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t1.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t2.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t3.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t4.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t5.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t6.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t7.s1.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x02",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t0.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t1.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t2.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t3.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t4.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t5.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t6.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t7.s2.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x04",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t0.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t1.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t2.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t3.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t4.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t5.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t6.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t7.s3.rdblkc_s",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x08",
  "UMask": "0x08"
 },
 {
  "EventName": "l3fillvicreq.t0.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t1.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t2.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t3.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t4.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t5.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t6.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t7.s0.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x01",
  "UMask": "0x10"
 },
 
 {
  "EventName": "l3fillvicreq.t0.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t1.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t2.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t3.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t4.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t5.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t6.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t7.s1.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x02",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t0.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t1.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t2.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t3.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t4.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t5.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t6.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t7.s2.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x04",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t0.s3.rdblkx_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t1.s3.rdblkx_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t2.s3.rdblkx_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t3.s3.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t4.s3.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t5.s3.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t6.s3.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t7.s3.rdblkx_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x08",
  "UMask": "0x10"
 },
 {
  "EventName": "l3fillvicreq.t0.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t1.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t2.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t3.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t4.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t5.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t6.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t7.s0.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x01",
  "UMask": "0x20"
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 {
  "EventName": "l3fillvicreq.t0.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t1.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t2.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t3.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t4.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t5.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t6.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t7.s1.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x02",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t0.s2.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t1.s2.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t2.s2.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t3.s2.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t4.s2.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t5.s2.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t6.s2.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t7.s2.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x04",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t0.s3.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x08",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t1.s3.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
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  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t2.s3.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
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  "UMask": "0x20"
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 {
  "EventName": "l3fillvicreq.t3.s3.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
  "L3SliceMask": "0x08",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t4.s3.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
  "L3SliceMask": "0x08",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t5.s3.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
  "L3SliceMask": "0x08",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t6.s3.rdblkx",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
  "L3SliceMask": "0x08",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t7.s3.rdblkx",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
  "L3SliceMask": "0x08",
  "UMask": "0x20"
 },
 {
  "EventName": "l3fillvicreq.t0.s0.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x01",
  "L3SliceMask": "0x01",
  "UMask": "0x40"
 },
 {
  "EventName": "l3fillvicreq.t1.s0.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
  "L3SliceMask": "0x01",
  "UMask": "0x40"
 },
 {
  "EventName": "l3fillvicreq.t2.s0.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x04",
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  "UMask": "0x40"
 },
 {
  "EventName": "l3fillvicreq.t3.s0.rdblkl_vic",
  "EventCode": "0x03",
  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
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  "UMask": "0x40"
 },
 {
  "EventName": "l3fillvicreq.t4.s0.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
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  "UMask": "0x40"
 },
 {
  "EventName": "l3fillvicreq.t5.s0.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
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  "UMask": "0x40"
 },
 {
  "EventName": "l3fillvicreq.t6.s0.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
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 {
  "EventName": "l3fillvicreq.t7.s0.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
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 {
  "EventName": "l3fillvicreq.t0.s1.rdblkl_vic",
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 {
  "EventName": "l3fillvicreq.t1.s1.rdblkl_vic",
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  "L3ThreadMask": "0x02",
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 },
 {
  "EventName": "l3fillvicreq.t2.s1.rdblkl_vic",
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  "L3ThreadMask": "0x04",
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 },
 {
  "EventName": "l3fillvicreq.t3.s1.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
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 },
 {
  "EventName": "l3fillvicreq.t4.s1.rdblkl_vic",
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  "L3ThreadMask": "0x10",
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 },
 {
  "EventName": "l3fillvicreq.t5.s1.rdblkl_vic",
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  "L3ThreadMask": "0x20",
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 },
 {
  "EventName": "l3fillvicreq.t6.s1.rdblkl_vic",
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  "L3ThreadMask": "0x40",
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 },
 {
  "EventName": "l3fillvicreq.t7.s1.rdblkl_vic",
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  "L3ThreadMask": "0x80",
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 },
 {
  "EventName": "l3fillvicreq.t0.s2.rdblkl_vic",
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  "L3ThreadMask": "0x01",
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 },
 {
  "EventName": "l3fillvicreq.t1.s2.rdblkl_vic",
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 },
 {
  "EventName": "l3fillvicreq.t2.s2.rdblkl_vic",
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 },
 {
  "EventName": "l3fillvicreq.t3.s2.rdblkl_vic",
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  "L3ThreadMask": "0x08",
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 },
 {
  "EventName": "l3fillvicreq.t4.s2.rdblkl_vic",
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  "L3ThreadMask": "0x10",
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 },
 {
  "EventName": "l3fillvicreq.t5.s2.rdblkl_vic",
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  "L3ThreadMask": "0x20",
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 },
 {
  "EventName": "l3fillvicreq.t6.s2.rdblkl_vic",
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  "L3ThreadMask": "0x40",
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 },
 {
  "EventName": "l3fillvicreq.t7.s2.rdblkl_vic",
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  "L3ThreadMask": "0x80",
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 },
 {
  "EventName": "l3fillvicreq.t0.s3.rdblkl_vic",
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  "L3ThreadMask": "0x01",
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 },
 {
  "EventName": "l3fillvicreq.t1.s3.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x02",
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 },
 {
  "EventName": "l3fillvicreq.t2.s3.rdblkl_vic",
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 },
 {
  "EventName": "l3fillvicreq.t3.s3.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x08",
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 },
 {
  "EventName": "l3fillvicreq.t4.s3.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x10",
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 },
 {
  "EventName": "l3fillvicreq.t5.s3.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x20",
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 },
 {
  "EventName": "l3fillvicreq.t6.s3.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x40",
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  "UMask": "0x40"
 },
 {
  "EventName": "l3fillvicreq.t7.s3.rdblkl_vic",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
  "L3ThreadMask": "0x80",
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 },
 {
  "EventName": "l3fillvicreq.t0.s0.rdblkl",
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  "L3ThreadMask": "0x01",
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 {
  "EventName": "l3fillvicreq.t1.s0.rdblkl",
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  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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 {
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]