.\"	$OpenBSD: arm_sync_icache.2,v 1.4 2013/08/14 06:32:26 jmc Exp $
.\"	$NetBSD: arm_sync_icache.2,v 1.5 2004/02/13 09:56:47 wiz Exp $
.\"
.\" Copyright (c) 1996 Mark Brinicombe
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.Dd $Mdocdate: August 14 2013 $
.Dt ARM_SYNC_ICACHE 2 arm
.Os
.Sh NAME
.Nm arm_sync_icache
.Nd clean the CPU data cache and flush the CPU instruction cache
.Sh SYNOPSIS
.In machine/sysarch.h
.Ft int
.Fn arm_sync_icache "u_int addr" "int len"
.Sh DESCRIPTION
.Fn arm_sync_icache
will make sure that all the entries in the processor instruction cache
are synchronized with main memory and that any data in a write back cache
has been cleaned.
Some ARM processors (e.g. SA110) have separate instruction and data
caches, thus any dynamically generated or modified code needs to be
written back from any data caches to main memory and the instruction
cache needs to be synchronized with main memory.
.Pp
On such processors,
.Fn arm_sync_icache
will clean the data cache and invalidate the processor instruction cache
to force reloading from main memory.
On processors that have a shared instruction and data cache and have a
write through cache (e.g. ARM6), no action needs to be taken.
.Pp
The routine takes a start address
.Fa addr
and a length
.Fa len
to describe the area of memory that needs to be cleaned and synchronized.
.Sh ERRORS
.Fn arm_sync_icache
will never fail so will always return 0.
.Sh REFERENCES
StrongARM Data Sheet